forked from OSchip/llvm-project
167 lines
4.2 KiB
LLVM
167 lines
4.2 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify %s | FileCheck -check-prefix=IR %s
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; SI-LABEL: {{^}}infinite_loop:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
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; SI: [[LOOP:BB[0-9]+_[0-9]+]]: ; %loop
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG]]
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; SI: s_branch [[LOOP]]
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define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) {
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entry:
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br label %loop
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loop:
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store volatile i32 999, i32 addrspace(1)* %out, align 4
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br label %loop
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}
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; IR-LABEL: @infinite_loop_ret(
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; IR: br i1 %cond, label %loop, label %UnifiedReturnBlock
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; IR: loop:
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; IR: store volatile i32 999, i32 addrspace(1)* %out, align 4
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; IR: br i1 true, label %loop, label %UnifiedReturnBlock
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; IR: UnifiedReturnBlock:
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; IR: ret void
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; SI-LABEL: {{^}}infinite_loop_ret:
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; SI: s_cbranch_execz [[RET:BB[0-9]+_[0-9]+]]
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
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; SI: [[LOOP:BB[0-9]+_[0-9]+]]: ; %loop
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; SI: s_and_b64 vcc, exec, -1
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG]]
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; SI: s_cbranch_execnz [[LOOP]]
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; SI: [[RET]]: ; %UnifiedReturnBlock
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; SI: s_endpgm
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define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) {
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%cond = icmp eq i32 %tmp, 1
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br i1 %cond, label %loop, label %return
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loop:
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store volatile i32 999, i32 addrspace(1)* %out, align 4
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br label %loop
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return:
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ret void
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}
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; IR-LABEL: @infinite_loops(
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; IR: br i1 undef, label %loop1, label %loop2
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; IR: loop1:
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; IR: store volatile i32 999, i32 addrspace(1)* %out, align 4
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; IR: br i1 true, label %loop1, label %DummyReturnBlock
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; IR: loop2:
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; IR: store volatile i32 888, i32 addrspace(1)* %out, align 4
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; IR: br i1 true, label %loop2, label %DummyReturnBlock
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; IR: DummyReturnBlock:
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; IR: ret void
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; SI-LABEL: {{^}}infinite_loops:
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; SI: v_mov_b32_e32 [[REG1:v[0-9]+]], 0x3e7
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; SI: s_and_b64 vcc, exec, -1
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; SI: [[LOOP1:BB[0-9]+_[0-9]+]]: ; %loop1
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG1]]
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; SI: s_cbranch_vccnz [[LOOP1]]
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; SI: s_branch [[RET:BB[0-9]+_[0-9]+]]
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; SI: v_mov_b32_e32 [[REG2:v[0-9]+]], 0x378
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; SI: s_and_b64 vcc, exec, -1
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; SI: [[LOOP2:BB[0-9]+_[0-9]+]]: ; %loop2
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG2]]
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; SI: s_cbranch_vccnz [[LOOP2]]
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; SI: [[RET]]: ; %DummyReturnBlock
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; SI: s_endpgm
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define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) {
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entry:
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br i1 undef, label %loop1, label %loop2
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loop1:
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store volatile i32 999, i32 addrspace(1)* %out, align 4
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br label %loop1
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loop2:
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store volatile i32 888, i32 addrspace(1)* %out, align 4
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br label %loop2
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}
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; IR-LABEL: @infinite_loop_nest_ret(
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; IR: br i1 %cond1, label %outer_loop, label %UnifiedReturnBlock
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; IR: outer_loop:
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; IR: br label %inner_loop
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; IR: inner_loop:
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; IR: store volatile i32 999, i32 addrspace(1)* %out, align 4
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; IR: %cond3 = icmp eq i32 %tmp, 3
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; IR: br i1 true, label %TransitionBlock, label %UnifiedReturnBlock
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; IR: TransitionBlock:
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; IR: br i1 %cond3, label %inner_loop, label %outer_loop
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; IR: UnifiedReturnBlock:
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; IR: ret void
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; SI-LABEL: {{^}}infinite_loop_nest_ret:
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; SI: s_cbranch_execz [[RET:BB[0-9]+_[0-9]+]]
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; SI: s_mov_b32
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; SI: [[OUTER_LOOP:BB[0-9]+_[0-9]+]]: ; %outer_loop
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; SI: [[INNER_LOOP:BB[0-9]+_[0-9]+]]: ; %inner_loop
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; SI: s_waitcnt expcnt(0)
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
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; SI: s_waitcnt lgkmcnt(0)
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; SI: buffer_store_dword [[REG]]
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; SI: s_andn2_b64 exec
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; SI: s_cbranch_execnz [[INNER_LOOP]]
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; SI: s_andn2_b64 exec
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; SI: s_cbranch_execnz [[OUTER_LOOP]]
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; SI: [[RET]]: ; %UnifiedReturnBlock
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; SI: s_endpgm
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define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) {
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%cond1 = icmp eq i32 %tmp, 1
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br i1 %cond1, label %outer_loop, label %return
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outer_loop:
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; %cond2 = icmp eq i32 %tmp, 2
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; br i1 %cond2, label %outer_loop, label %inner_loop
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br label %inner_loop
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inner_loop: ; preds = %LeafBlock, %LeafBlock1
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store volatile i32 999, i32 addrspace(1)* %out, align 4
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%cond3 = icmp eq i32 %tmp, 3
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br i1 %cond3, label %inner_loop, label %outer_loop
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return:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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