forked from OSchip/llvm-project
67 lines
2.0 KiB
LLVM
67 lines
2.0 KiB
LLVM
; RUN: llc -O0 -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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; FIXME: Merge into indirect-addressing-si.ll
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; Make sure that TwoAddressInstructions keeps src0 as subregister sub0
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; of the tied implicit use and def of the super register.
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; CHECK-LABEL: {{^}}insert_wo_offset:
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; CHECK: s_load_dword [[IN:s[0-9]+]]
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; CHECK: s_mov_b32 m0, [[IN]]
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; CHECK: v_movreld_b32_e32 v[[ELT0:[0-9]+]]
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; CHECK-NEXT: buffer_store_dwordx4 v{{\[}}[[ELT0]]:
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define amdgpu_kernel void @insert_wo_offset(<4 x float> addrspace(1)* %out, i32 %in) {
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entry:
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%ins = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in
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store <4 x float> %ins, <4 x float> addrspace(1)* %out
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ret void
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}
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; Make sure we don't hit use of undefined register errors when expanding an
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; extract with undef index.
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; CHECK-LABEL: {{^}}extract_adjacent_blocks:
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; CHECK: s_load_dword [[ARG:s[0-9]+]]
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; CHECK: s_cmp_lg_u32
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; CHECK: s_cbranch_scc1 [[BB4:BB[0-9]+_[0-9]+]]
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; CHECK: buffer_load_dwordx4
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; CHECK: v_cndmask_b32_e64
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; CHECK: v_cndmask_b32_e64
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; CHECK: v_cndmask_b32_e64
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; CHECK: s_branch [[ENDBB:BB[0-9]+_[0-9]+]]
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; CHECK: [[BB4]]:
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; CHECK: buffer_load_dwordx4
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; CHECK: v_cndmask_b32_e64
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; CHECK: v_cndmask_b32_e64
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; CHECK: v_cndmask_b32_e64
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; CHECK: [[ENDBB]]:
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; CHECK: buffer_store_dword
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; CHECK: s_endpgm
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define amdgpu_kernel void @extract_adjacent_blocks(i32 %arg) #0 {
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bb:
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%tmp = icmp eq i32 %arg, 0
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br i1 %tmp, label %bb1, label %bb4
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bb1:
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%tmp2 = load volatile <4 x float>, <4 x float> addrspace(1)* undef
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%tmp3 = extractelement <4 x float> %tmp2, i32 undef
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call void asm sideeffect "; reg use $0", "v"(<4 x float> %tmp2) #0 ; Prevent block optimize out
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br label %bb7
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bb4:
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%tmp5 = load volatile <4 x float>, <4 x float> addrspace(1)* undef
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%tmp6 = extractelement <4 x float> %tmp5, i32 undef
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call void asm sideeffect "; reg use $0", "v"(<4 x float> %tmp5) #0 ; Prevent block optimize out
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br label %bb7
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bb7:
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%tmp8 = phi float [ %tmp3, %bb1 ], [ %tmp6, %bb4 ]
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store volatile float %tmp8, float addrspace(1)* undef
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ret void
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}
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