forked from OSchip/llvm-project
309 lines
11 KiB
TableGen
309 lines
11 KiB
TableGen
//===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file contains the required infrastructure to support code generation
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/// for the standard 'V' (Vector) extension, version 0.9. This version is still
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/// experimental as the 'V' extension hasn't been ratified yet.
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///
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/// This file is included from RISCVInstrInfoV.td
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Utilities.
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//===----------------------------------------------------------------------===//
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// This class describes information associated to the LMUL.
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class LMULInfo<int lmul, VReg regclass, string mx> {
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bits<3> value = lmul; // This is encoded as the vlmul field of vtype.
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VReg vrclass = regclass;
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string MX = mx;
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}
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// Associate LMUL with tablegen records of register classes.
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def V_M1 : LMULInfo<0b000, VR, "M1">;
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def V_M2 : LMULInfo<0b001, VRM2, "M2">;
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def V_M4 : LMULInfo<0b010, VRM4, "M4">;
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def V_M8 : LMULInfo<0b011, VRM8, "M8">;
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def V_MF8 : LMULInfo<0b101, VR, "MF8">;
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def V_MF4 : LMULInfo<0b110, VR, "MF4">;
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def V_MF2 : LMULInfo<0b111, VR, "MF2">;
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// Used to iterate over all possible LMULs.
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def MxList {
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list<LMULInfo> m = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
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}
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class shift_amount<int num> {
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int val = !if(!eq(num, 1), 0, !add(1, shift_amount<!srl(num, 1)>.val));
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}
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// Output pattern for X0 used to represent VLMAX in the pseudo instructions.
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def VLMax : OutPatFrag<(ops), (XLenVT X0)>;
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// List of EEW.
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defvar EEWList = [8, 16, 32, 64];
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//===----------------------------------------------------------------------===//
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// Vector register and vector group type information.
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//===----------------------------------------------------------------------===//
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class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M>
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{
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ValueType Vector = Vec;
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ValueType Mask = Mas;
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int SEW = Sew;
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VReg RegClass = Reg;
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LMULInfo LMul = M;
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}
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class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas,
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int Sew, VReg Reg, LMULInfo M>
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: VTypeInfo<Vec, Mas, Sew, Reg, M>
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{
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ValueType VectorM1 = VecM1;
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}
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defset list<VTypeInfo> AllVectors = {
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defset list<VTypeInfo> AllIntegerVectors = {
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def : VTypeInfo<vint8mf8_t, vbool64_t, 8, VR, V_MF8>;
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def : VTypeInfo<vint8mf4_t, vbool32_t, 8, VR, V_MF4>;
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def : VTypeInfo<vint8mf2_t, vbool16_t, 8, VR, V_MF2>;
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def : VTypeInfo<vint8m1_t, vbool8_t, 8, VR, V_M1>;
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def : VTypeInfo<vint16mf4_t, vbool64_t, 16, VR, V_MF4>;
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def : VTypeInfo<vint16mf2_t, vbool32_t, 16, VR, V_MF2>;
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def : VTypeInfo<vint16m1_t, vbool16_t, 16, VR, V_M1>;
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def : VTypeInfo<vint32mf2_t, vbool64_t, 32, VR, V_MF2>;
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def : VTypeInfo<vint32m1_t, vbool32_t, 32, VR, V_M1>;
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def : VTypeInfo<vint64m1_t, vbool64_t, 64, VR, V_M1>;
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def : GroupVTypeInfo<vint8m2_t, vint8m1_t, vbool4_t, 8, VRM2, V_M2>;
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def : GroupVTypeInfo<vint8m4_t, vint8m1_t, vbool2_t, 8, VRM4, V_M4>;
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def : GroupVTypeInfo<vint8m8_t, vint8m1_t, vbool1_t, 8, VRM8, V_M8>;
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def : GroupVTypeInfo<vint16m2_t,vint16m1_t,vbool8_t, 16,VRM2, V_M2>;
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def : GroupVTypeInfo<vint16m4_t,vint16m1_t,vbool4_t, 16,VRM4, V_M4>;
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def : GroupVTypeInfo<vint16m8_t,vint16m1_t,vbool2_t, 16,VRM8, V_M8>;
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def : GroupVTypeInfo<vint32m2_t,vint32m1_t,vbool16_t,32,VRM2, V_M2>;
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def : GroupVTypeInfo<vint32m4_t,vint32m1_t,vbool8_t, 32,VRM4, V_M4>;
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def : GroupVTypeInfo<vint32m8_t,vint32m1_t,vbool4_t, 32,VRM8, V_M8>;
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def : GroupVTypeInfo<vint64m2_t,vint64m1_t,vbool32_t,64,VRM2, V_M2>;
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def : GroupVTypeInfo<vint64m4_t,vint64m1_t,vbool16_t,64,VRM4, V_M4>;
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def : GroupVTypeInfo<vint64m8_t,vint64m1_t,vbool8_t, 64,VRM8, V_M8>;
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}
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}
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// This class holds the record of the RISCVVPseudoTable below.
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// This represents the information we need in codegen for each pseudo.
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class RISCVVPseudo {
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Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
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Instruction BaseInstr;
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bits<8> VLIndex;
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bits<8> SEWIndex;
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bits<8> MergeOpIndex;
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bits<3> VLMul;
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}
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// The actual table.
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def RISCVVPseudosTable : GenericTable {
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let FilterClass = "RISCVVPseudo";
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let CppTypeName = "PseudoInfo";
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let Fields = [ "Pseudo", "BaseInstr", "VLIndex", "SEWIndex", "MergeOpIndex",
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"VLMul" ];
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let PrimaryKey = [ "Pseudo" ];
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let PrimaryKeyName = "getPseudoInfo";
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}
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//===----------------------------------------------------------------------===//
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// Helpers to define the different pseudo instructions.
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//===----------------------------------------------------------------------===//
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multiclass pseudo_binary<VReg result_reg_class,
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VReg op1_reg_class,
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DAGOperand op2_kind,
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LMULInfo vlmul > {
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let Constraints = "$rd = $merge",
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Uses = [VL, VTYPE], VLIndex = 5, SEWIndex = 6, MergeOpIndex = 1,
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BaseInstr = !cast<Instruction>(!subst("Pseudo", "", NAME)) in
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def "_"# vlmul.MX : Pseudo<(outs result_reg_class:$rd),
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(ins result_reg_class:$merge,
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op1_reg_class:$rs2, op2_kind:$rs1,
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VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),
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[]>,
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RISCVVPseudo;
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}
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multiclass pseudo_binary_v_vv_vx_vi<Operand imm_type = simm5,
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bit force_earlyclobber = 0> {
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1 in
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foreach m = MxList.m in
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{
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let VLMul = m.value in
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{
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defvar evr = m.vrclass;
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defm _VV : pseudo_binary<evr, evr, evr, m>;
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defm _VX : pseudo_binary<evr, evr, GPR, m>;
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defm _VI : pseudo_binary<evr, evr, imm_type, m>;
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// Helpers to define the different patterns.
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//===----------------------------------------------------------------------===//
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multiclass pat_vop_binary<SDNode vop,
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string instruction_name,
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ValueType result_type,
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ValueType op_type,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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VReg result_reg_class,
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VReg op_reg_class,
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bit swap = 0>
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{
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defvar instruction = !cast<Instruction>(instruction_name#"_VV_"# vlmul.MX);
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def : Pat<(result_type (vop
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(op_type op_reg_class:$rs1),
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(op_type op_reg_class:$rs2))),
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(instruction (result_type (IMPLICIT_DEF)),
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op_reg_class:$rs1,
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op_reg_class:$rs2,
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(mask_type zero_reg),
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VLMax, sew)>;
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}
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multiclass pat_vop_binary_common<SDNode vop,
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string instruction_name,
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list<VTypeInfo> vtilist>
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{
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foreach vti = vtilist in
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defm : pat_vop_binary<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass>;
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instructions and patterns.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtV] in {
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//===----------------------------------------------------------------------===//
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// 6. Configuration-Setting Instructions
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//===----------------------------------------------------------------------===//
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// Pseudos.
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0, Defs = [VL, VTYPE] in {
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def PseudoVSETVLI : Pseudo<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei), []>;
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}
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//===----------------------------------------------------------------------===//
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// 7. Vector Loads and Stores
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//===----------------------------------------------------------------------===//
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// Pseudos.
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foreach eew = EEWList in {
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foreach lmul = MxList.m in {
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defvar LInfo = lmul.MX;
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defvar vreg = lmul.vrclass;
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defvar vlmul = lmul.value;
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defvar constraint = "$rd = $merge";
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let mayLoad = 1, mayStore = 0, hasSideEffects = 0,
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usesCustomInserter = 1,
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VLMul = vlmul in
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{
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let Uses = [VL, VTYPE], VLIndex = 4, SEWIndex = 5, MergeOpIndex = 1,
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Constraints = constraint,
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BaseInstr = !cast<Instruction>("VLE" # eew # "_V") in
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def "PseudoVLE" # eew # "_V_" # LInfo
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: Pseudo<(outs vreg:$rd),
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(ins vreg:$merge, GPR:$rs1, VMaskOp:$mask, GPR:$vl,
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ixlenimm:$sew),
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[]>,
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RISCVVPseudo;
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}
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let mayLoad = 0, mayStore = 1, hasSideEffects = 0,
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usesCustomInserter = 1,
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VLMul = vlmul in
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{
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// Masked stores do not have a merge operand as merge is done in memory
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let Uses = [VL, VTYPE],
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VLIndex = 3, SEWIndex = 4, MergeOpIndex = -1,
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BaseInstr = !cast<Instruction>("VSE" # eew # "_V") in
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def "PseudoVSE" # eew # "_V_" # LInfo
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: Pseudo<(outs),
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(ins vreg:$rd, GPR:$rs1, VMaskOp:$mask, GPR:$vl,
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ixlenimm:$sew),
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[]>,
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RISCVVPseudo;
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}
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}
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}
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// Patterns.
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multiclass pat_load_store<LLVMType type,
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LLVMType mask_type,
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int sew,
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LMULInfo vlmul,
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VReg reg_class>
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{
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defvar load_instr = !cast<Instruction>("PseudoVLE" # sew # "_V_"# vlmul.MX);
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defvar store_instr = !cast<Instruction>("PseudoVSE" # sew # "_V_"# vlmul.MX);
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// Load
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def : Pat<(type (load GPR:$rs1)),
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(load_instr (type (IMPLICIT_DEF)),
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GPR:$rs1,
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(mask_type zero_reg),
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VLMax, sew)>;
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def : Pat<(type (load AddrFI:$rs1)),
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(load_instr (type (IMPLICIT_DEF)),
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AddrFI:$rs1,
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(mask_type zero_reg),
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VLMax, sew)>;
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// Store
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def : Pat<(store type:$rs2, GPR:$rs1),
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(store_instr reg_class:$rs2, GPR:$rs1,
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(mask_type zero_reg),
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VLMax, sew)>;
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def : Pat<(store type:$rs2, AddrFI:$rs1),
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(store_instr reg_class:$rs2, AddrFI:$rs1,
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(mask_type zero_reg),
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VLMax, sew)>;
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}
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foreach vti = AllVectors in
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{
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defm : pat_load_store<vti.Vector, vti.Mask,
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vti.SEW, vti.LMul, vti.RegClass>;
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}
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//===----------------------------------------------------------------------===//
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// 12. Vector Integer Arithmetic Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// 12.1. Vector Single-Width Integer Add and Subtract
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//===----------------------------------------------------------------------===//
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// Pseudo instructions.
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defm PseudoVADD : pseudo_binary_v_vv_vx_vi;
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// Whole-register vector patterns.
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defm "" : pat_vop_binary_common<add, "PseudoVADD", AllIntegerVectors>;
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} // Predicates = [HasStdExtV]
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