forked from OSchip/llvm-project
530 lines
14 KiB
LLVM
530 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; Function Attrs: nounwind
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define zeroext i8 @_Z6testcff(float %arg) {
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; CHECK-LABEL: _Z6testcff:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfs f1, -4(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptoui float %0 to i8
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ret i8 %conv
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}
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; Function Attrs: nounwind
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define float @_Z6testfcc(i8 zeroext %arg) {
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; CHECK-LABEL: _Z6testfcc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stb r3, -1(r1)
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; CHECK-NEXT: xscvuxdsp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i8, align 1
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store i8 %arg, i8* %arg.addr, align 1
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%0 = load i8, i8* %arg.addr, align 1
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%conv = uitofp i8 %0 to float
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ret float %conv
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}
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; Function Attrs: nounwind
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define zeroext i8 @_Z6testcdd(double %arg) {
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; CHECK-LABEL: _Z6testcdd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfd f1, -8(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptoui double %0 to i8
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ret i8 %conv
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}
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; Function Attrs: nounwind
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define double @_Z6testdcc(i8 zeroext %arg) {
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; CHECK-LABEL: _Z6testdcc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stb r3, -1(r1)
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; CHECK-NEXT: xscvuxddp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i8, align 1
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store i8 %arg, i8* %arg.addr, align 1
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%0 = load i8, i8* %arg.addr, align 1
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%conv = uitofp i8 %0 to double
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ret double %conv
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}
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; Function Attrs: nounwind
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define zeroext i8 @_Z7testucff(float %arg) {
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; CHECK-LABEL: _Z7testucff:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfs f1, -4(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptoui float %0 to i8
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ret i8 %conv
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}
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; Function Attrs: nounwind
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define float @_Z7testfuch(i8 zeroext %arg) {
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; CHECK-LABEL: _Z7testfuch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stb r3, -1(r1)
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; CHECK-NEXT: xscvuxdsp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i8, align 1
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store i8 %arg, i8* %arg.addr, align 1
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%0 = load i8, i8* %arg.addr, align 1
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%conv = uitofp i8 %0 to float
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ret float %conv
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}
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; Function Attrs: nounwind
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define zeroext i8 @_Z7testucdd(double %arg) {
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; CHECK-LABEL: _Z7testucdd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfd f1, -8(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptoui double %0 to i8
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ret i8 %conv
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}
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; Function Attrs: nounwind
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define double @_Z7testduch(i8 zeroext %arg) {
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; CHECK-LABEL: _Z7testduch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stb r3, -1(r1)
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; CHECK-NEXT: xscvuxddp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i8, align 1
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store i8 %arg, i8* %arg.addr, align 1
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%0 = load i8, i8* %arg.addr, align 1
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%conv = uitofp i8 %0 to double
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ret double %conv
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}
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; Function Attrs: nounwind
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define signext i16 @_Z6testsff(float %arg) {
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; CHECK-LABEL: _Z6testsff:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfs f1, -4(r1)
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptosi float %0 to i16
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ret i16 %conv
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}
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; Function Attrs: nounwind
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define float @_Z6testfss(i16 signext %arg) {
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; CHECK-LABEL: _Z6testfss:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwa f0, r3
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; CHECK-NEXT: sth r3, -2(r1)
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; CHECK-NEXT: xscvsxdsp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i16, align 2
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store i16 %arg, i16* %arg.addr, align 2
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%0 = load i16, i16* %arg.addr, align 2
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%conv = sitofp i16 %0 to float
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ret float %conv
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}
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; Function Attrs: nounwind
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define signext i16 @_Z6testsdd(double %arg) {
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; CHECK-LABEL: _Z6testsdd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfd f1, -8(r1)
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptosi double %0 to i16
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ret i16 %conv
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}
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; Function Attrs: nounwind
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define double @_Z6testdss(i16 signext %arg) {
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; CHECK-LABEL: _Z6testdss:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwa f0, r3
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; CHECK-NEXT: sth r3, -2(r1)
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; CHECK-NEXT: xscvsxddp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i16, align 2
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store i16 %arg, i16* %arg.addr, align 2
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%0 = load i16, i16* %arg.addr, align 2
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%conv = sitofp i16 %0 to double
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ret double %conv
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}
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; Function Attrs: nounwind
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define zeroext i16 @_Z7testusff(float %arg) {
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; CHECK-LABEL: _Z7testusff:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfs f1, -4(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptoui float %0 to i16
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ret i16 %conv
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}
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; Function Attrs: nounwind
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define float @_Z7testfust(i16 zeroext %arg) {
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; CHECK-LABEL: _Z7testfust:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: sth r3, -2(r1)
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; CHECK-NEXT: xscvuxdsp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i16, align 2
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store i16 %arg, i16* %arg.addr, align 2
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%0 = load i16, i16* %arg.addr, align 2
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%conv = uitofp i16 %0 to float
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ret float %conv
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}
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; Function Attrs: nounwind
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define zeroext i16 @_Z7testusdd(double %arg) {
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; CHECK-LABEL: _Z7testusdd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfd f1, -8(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptoui double %0 to i16
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ret i16 %conv
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}
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; Function Attrs: nounwind
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define double @_Z7testdust(i16 zeroext %arg) {
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; CHECK-LABEL: _Z7testdust:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: sth r3, -2(r1)
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; CHECK-NEXT: xscvuxddp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i16, align 2
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store i16 %arg, i16* %arg.addr, align 2
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%0 = load i16, i16* %arg.addr, align 2
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%conv = uitofp i16 %0 to double
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ret double %conv
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}
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; Function Attrs: nounwind
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define signext i32 @_Z6testiff(float %arg) {
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; CHECK-LABEL: _Z6testiff:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfs f1, -4(r1)
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptosi float %0 to i32
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ret i32 %conv
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}
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; Function Attrs: nounwind
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define float @_Z6testfii(i32 signext %arg) {
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; CHECK-LABEL: _Z6testfii:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwa f0, r3
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; CHECK-NEXT: stw r3, -4(r1)
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; CHECK-NEXT: xscvsxdsp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i32, align 4
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store i32 %arg, i32* %arg.addr, align 4
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%0 = load i32, i32* %arg.addr, align 4
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%conv = sitofp i32 %0 to float
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ret float %conv
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}
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; Function Attrs: nounwind
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define signext i32 @_Z6testidd(double %arg) {
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; CHECK-LABEL: _Z6testidd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfd f1, -8(r1)
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptosi double %0 to i32
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ret i32 %conv
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}
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; Function Attrs: nounwind
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define double @_Z6testdii(i32 signext %arg) {
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; CHECK-LABEL: _Z6testdii:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwa f0, r3
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; CHECK-NEXT: stw r3, -4(r1)
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; CHECK-NEXT: xscvsxddp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i32, align 4
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store i32 %arg, i32* %arg.addr, align 4
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%0 = load i32, i32* %arg.addr, align 4
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%conv = sitofp i32 %0 to double
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ret double %conv
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}
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; Function Attrs: nounwind
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define zeroext i32 @_Z7testuiff(float %arg) {
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; CHECK-LABEL: _Z7testuiff:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpuxws f0, f1
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; CHECK-NEXT: stfs f1, -4(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptoui float %0 to i32
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ret i32 %conv
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}
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; Function Attrs: nounwind
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define float @_Z7testfuij(i32 zeroext %arg) {
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; CHECK-LABEL: _Z7testfuij:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stw r3, -4(r1)
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; CHECK-NEXT: xscvuxdsp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i32, align 4
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store i32 %arg, i32* %arg.addr, align 4
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%0 = load i32, i32* %arg.addr, align 4
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%conv = uitofp i32 %0 to float
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ret float %conv
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}
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; Function Attrs: nounwind
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define zeroext i32 @_Z7testuidd(double %arg) {
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; CHECK-LABEL: _Z7testuidd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpuxws f0, f1
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; CHECK-NEXT: stfd f1, -8(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptoui double %0 to i32
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ret i32 %conv
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}
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; Function Attrs: nounwind
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define double @_Z7testduij(i32 zeroext %arg) {
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; CHECK-LABEL: _Z7testduij:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stw r3, -4(r1)
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; CHECK-NEXT: xscvuxddp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i32, align 4
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store i32 %arg, i32* %arg.addr, align 4
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%0 = load i32, i32* %arg.addr, align 4
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%conv = uitofp i32 %0 to double
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ret double %conv
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}
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; Function Attrs: nounwind
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define i64 @_Z7testllff(float %arg) {
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; CHECK-LABEL: _Z7testllff:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxds f0, f1
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; CHECK-NEXT: stfs f1, -4(r1)
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; CHECK-NEXT: mffprd r3, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptosi float %0 to i64
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ret i64 %conv
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}
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; Function Attrs: nounwind
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define float @_Z7testfllx(i64 %arg) {
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; CHECK-LABEL: _Z7testfllx:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtfprd f0, r3
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; CHECK-NEXT: std r3, -8(r1)
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; CHECK-NEXT: xscvsxdsp f1, f0
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; CHECK-NEXT: blr
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entry:
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%arg.addr = alloca i64, align 8
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store i64 %arg, i64* %arg.addr, align 8
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%0 = load i64, i64* %arg.addr, align 8
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%conv = sitofp i64 %0 to float
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ret float %conv
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}
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; Function Attrs: nounwind
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define i64 @_Z7testlldd(double %arg) {
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; CHECK-LABEL: _Z7testlldd:
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; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: xscvdpsxds f0, f1
|
|
; CHECK-NEXT: stfd f1, -8(r1)
|
|
; CHECK-NEXT: mffprd r3, f0
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%arg.addr = alloca double, align 8
|
|
store double %arg, double* %arg.addr, align 8
|
|
%0 = load double, double* %arg.addr, align 8
|
|
%conv = fptosi double %0 to i64
|
|
ret i64 %conv
|
|
}
|
|
|
|
; Function Attrs: nounwind
|
|
define double @_Z7testdllx(i64 %arg) {
|
|
; CHECK-LABEL: _Z7testdllx:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: mtfprd f0, r3
|
|
; CHECK-NEXT: std r3, -8(r1)
|
|
; CHECK-NEXT: xscvsxddp f1, f0
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%arg.addr = alloca i64, align 8
|
|
store i64 %arg, i64* %arg.addr, align 8
|
|
%0 = load i64, i64* %arg.addr, align 8
|
|
%conv = sitofp i64 %0 to double
|
|
ret double %conv
|
|
}
|
|
|
|
; Function Attrs: nounwind
|
|
define i64 @_Z8testullff(float %arg) {
|
|
; CHECK-LABEL: _Z8testullff:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: xscvdpuxds f0, f1
|
|
; CHECK-NEXT: stfs f1, -4(r1)
|
|
; CHECK-NEXT: mffprd r3, f0
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%arg.addr = alloca float, align 4
|
|
store float %arg, float* %arg.addr, align 4
|
|
%0 = load float, float* %arg.addr, align 4
|
|
%conv = fptoui float %0 to i64
|
|
ret i64 %conv
|
|
}
|
|
|
|
; Function Attrs: nounwind
|
|
define float @_Z8testfully(i64 %arg) {
|
|
; CHECK-LABEL: _Z8testfully:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: mtfprd f0, r3
|
|
; CHECK-NEXT: std r3, -8(r1)
|
|
; CHECK-NEXT: xscvuxdsp f1, f0
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%arg.addr = alloca i64, align 8
|
|
store i64 %arg, i64* %arg.addr, align 8
|
|
%0 = load i64, i64* %arg.addr, align 8
|
|
%conv = uitofp i64 %0 to float
|
|
ret float %conv
|
|
}
|
|
|
|
; Function Attrs: nounwind
|
|
define i64 @_Z8testulldd(double %arg) {
|
|
; CHECK-LABEL: _Z8testulldd:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: xscvdpuxds f0, f1
|
|
; CHECK-NEXT: stfd f1, -8(r1)
|
|
; CHECK-NEXT: mffprd r3, f0
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%arg.addr = alloca double, align 8
|
|
store double %arg, double* %arg.addr, align 8
|
|
%0 = load double, double* %arg.addr, align 8
|
|
%conv = fptoui double %0 to i64
|
|
ret i64 %conv
|
|
}
|
|
|
|
; Function Attrs: nounwind
|
|
define double @_Z8testdully(i64 %arg) {
|
|
; CHECK-LABEL: _Z8testdully:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: mtfprd f0, r3
|
|
; CHECK-NEXT: std r3, -8(r1)
|
|
; CHECK-NEXT: xscvuxddp f1, f0
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%arg.addr = alloca i64, align 8
|
|
store i64 %arg, i64* %arg.addr, align 8
|
|
%0 = load i64, i64* %arg.addr, align 8
|
|
%conv = uitofp i64 %0 to double
|
|
ret double %conv
|
|
}
|