| .. |
|
AsmParser
|
[RISCV] Prevent assertion in the assembler if vmerge or vfmerge are given a V0 destination.
|
2020-12-14 17:22:55 -08:00 |
|
Disassembler
|
[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
|
MCTargetDesc
|
[RISCV] Move vtype decoding and printing from RISCVInstPrinter to RISCVBaseInfo. Share with the assembly parser's debug output
|
2020-12-14 10:50:26 -08:00 |
|
TargetInfo
|
llvmbuildectomy - replace llvm-build by plain cmake
|
2020-11-13 10:35:24 +01:00 |
|
Utils
|
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
|
2020-12-15 12:56:49 +08:00 |
|
CMakeLists.txt
|
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
|
2020-12-11 10:35:37 -08:00 |
|
RISCV.h
|
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
|
2020-12-11 10:35:37 -08:00 |
|
RISCV.td
|
[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
|
2020-12-10 19:25:51 +00:00 |
|
RISCVAsmPrinter.cpp
|
[RISCV] Add -mtune support
|
2020-10-16 13:55:08 +08:00 |
|
RISCVCallLowering.cpp
|
…
|
|
|
RISCVCallLowering.h
|
…
|
|
|
RISCVCallingConv.td
|
…
|
|
|
RISCVCleanupVSETVLI.cpp
|
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
|
2020-12-11 10:35:37 -08:00 |
|
RISCVExpandAtomicPseudoInsts.cpp
|
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
|
2020-07-15 10:50:55 +01:00 |
|
RISCVExpandPseudoInsts.cpp
|
[RISCV] Initial infrastructure for code generation of the RISC-V V-extension
|
2020-12-04 11:39:30 -08:00 |
|
RISCVFrameLowering.cpp
|
[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
|
RISCVFrameLowering.h
|
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
|
2020-11-05 11:02:18 +00:00 |
|
RISCVISelDAGToDAG.cpp
|
[RISCV] Use SDLoc created early in RISCVDAGToDAGISel::Select instead of recreating it in multiple cases in the switch. NFC
|
2020-12-08 21:13:25 -08:00 |
|
RISCVISelDAGToDAG.h
|
[RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb.
|
2020-11-20 10:25:47 -08:00 |
|
RISCVISelLowering.cpp
|
[RISCV] Only custom legalize i32 arguments to vector intrinsics on RV64.
|
2020-12-15 13:54:41 -08:00 |
|
RISCVISelLowering.h
|
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
|
2020-12-15 12:56:49 +08:00 |
|
RISCVInstrFormats.td
|
Upgrade MC to v0.9.
|
2020-08-01 07:42:06 +08:00 |
|
RISCVInstrFormatsC.td
|
…
|
|
|
RISCVInstrFormatsV.td
|
[RISCV] add the MC layer support of riscv vector Zvamo extension
|
2020-08-27 14:11:38 +08:00 |
|
RISCVInstrInfo.cpp
|
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
|
2020-12-15 12:56:49 +08:00 |
|
RISCVInstrInfo.h
|
[RISCV] Don't include CodeGen layer files in MC layer
|
2020-11-12 07:45:38 -08:00 |
|
RISCVInstrInfo.td
|
[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
|
2020-12-10 19:25:51 +00:00 |
|
RISCVInstrInfoA.td
|
RISCV: Avoid GlobalISel build break in a future patch
|
2020-07-13 14:01:57 -04:00 |
|
RISCVInstrInfoB.td
|
[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
|
2020-12-10 19:25:51 +00:00 |
|
RISCVInstrInfoC.td
|
[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
|
2020-12-04 10:34:12 -08:00 |
|
RISCVInstrInfoD.td
|
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
|
2020-12-10 09:15:52 -08:00 |
|
RISCVInstrInfoF.td
|
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
|
2020-12-10 09:15:52 -08:00 |
|
RISCVInstrInfoM.td
|
[RISCV] Don't remove (and X, 0xffffffff) from inputs when matching RISCVISD::DIVUW/REMUW to 64-bit DIVU/REMU.
|
2020-11-26 23:15:41 -08:00 |
|
RISCVInstrInfoV.td
|
[RISCV] Initial infrastructure for code generation of the RISC-V V-extension
|
2020-12-04 11:39:30 -08:00 |
|
RISCVInstrInfoVPseudos.td
|
[RISCV] Define vnsrl/vnsra intrinsics.
|
2020-12-16 06:31:47 +08:00 |
|
RISCVInstrInfoZfh.td
|
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
|
2020-12-10 09:15:52 -08:00 |
|
RISCVInstructionSelector.cpp
|
RISCV: Avoid GlobalISel build break in a future patch
|
2020-07-13 14:01:57 -04:00 |
|
RISCVLegalizerInfo.cpp
|
…
|
|
|
RISCVLegalizerInfo.h
|
…
|
|
|
RISCVMCInstLower.cpp
|
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
|
2020-12-15 12:56:49 +08:00 |
|
RISCVMachineFunctionInfo.h
|
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
|
2020-07-01 07:28:11 +00:00 |
|
RISCVMergeBaseOffset.cpp
|
[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
|
RISCVRegisterBankInfo.cpp
|
…
|
|
|
RISCVRegisterBankInfo.h
|
…
|
|
|
RISCVRegisterBanks.td
|
…
|
|
|
RISCVRegisterInfo.cpp
|
[RISCV] Initial infrastructure for code generation of the RISC-V V-extension
|
2020-12-04 11:39:30 -08:00 |
|
RISCVRegisterInfo.h
|
…
|
|
|
RISCVRegisterInfo.td
|
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
|
2020-12-15 20:15:06 +08:00 |
|
RISCVSchedRocket.td
|
[RISCV] Fix formatting (NFC)
|
2020-09-25 18:15:04 -05:00 |
|
RISCVSchedSiFive7.td
|
[RISCV] Use the commercial name for scheduling model (NFC)
|
2020-10-23 16:33:27 -05:00 |
|
RISCVSchedule.td
|
[RISCV] Fix formatting (NFC)
|
2020-09-25 18:15:04 -05:00 |
|
RISCVSubtarget.cpp
|
[RISCV] Add -mtune support
|
2020-10-16 13:55:08 +08:00 |
|
RISCVSubtarget.h
|
[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
|
RISCVSystemOperands.td
|
[RISCV] Enable the use of the old mucounteren name
|
2020-08-17 13:11:49 +01:00 |
|
RISCVTargetMachine.cpp
|
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
|
2020-12-11 10:35:37 -08:00 |
|
RISCVTargetMachine.h
|
…
|
|
|
RISCVTargetObjectFile.cpp
|
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
|
2020-05-21 15:23:29 -07:00 |
|
RISCVTargetObjectFile.h
|
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
|
2020-05-21 15:23:29 -07:00 |
|
RISCVTargetTransformInfo.cpp
|
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
|
2020-09-22 11:54:10 +00:00 |
|
RISCVTargetTransformInfo.h
|
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
|
2020-09-22 11:54:10 +00:00 |
fd27164563