forked from OSchip/llvm-project
93 lines
3.7 KiB
YAML
93 lines
3.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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# RUN: llc -mtriple riscv64 -mattr=+m,+experimental-v -start-before=prologepilog -o - \
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# RUN: -verify-machineinstrs %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"
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define void @spillslot() {
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; CHECK-LABEL: spillslot:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -2032
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; CHECK-NEXT: .cfi_def_cfa_offset 2032
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; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset ra, -8
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; CHECK-NEXT: .cfi_offset s0, -16
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; CHECK-NEXT: addi s0, sp, 2032
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; CHECK-NEXT: .cfi_def_cfa s0, 0
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; CHECK-NEXT: addi sp, sp, -272
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; CHECK-NEXT: sd a0, 8(sp)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: sd a1, 0(sp)
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; CHECK-NEXT: lui a1, 1
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; CHECK-NEXT: addiw a1, a1, -1024
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; CHECK-NEXT: mul a0, a0, a1
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; CHECK-NEXT: ld a1, 0(sp)
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; CHECK-NEXT: sub sp, sp, a0
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; CHECK-NEXT: andi sp, sp, -128
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; CHECK-NEXT: lui a0, 1
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; CHECK-NEXT: addiw a0, a0, -1808
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
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; CHECK-NEXT: ld a0, 8(sp)
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; CHECK-NEXT: call spillslot@plt
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; CHECK-NEXT: lui a0, 1
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; CHECK-NEXT: addiw a0, a0, -1792
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; CHECK-NEXT: sub sp, s0, a0
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; CHECK-NEXT: addi sp, sp, 272
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; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 2032
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; CHECK-NEXT: ret
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ret void
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}
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...
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---
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name: spillslot
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alignment: 4
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tracksRegLiveness: false
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 128
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: default, offset: 0, size: 2048, alignment: 128,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: 0, size: 24576, alignment: 8,
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stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0:
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liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31, $v25
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PseudoVSPILL_M1 killed renamable $v25, %stack.1 :: (store unknown-size into %stack.1, align 8)
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; This is here just to make all the eligible registers live at this point.
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; This way when we replace the frame index %stack.1 with its actual address
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; we have to allocate two virtual registers to compute it.
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; A later run of the the register scavenger won't find available registers
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; either so it will have to spill two to the emergency spill slots
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; required for this RVV computation.
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PseudoCALL target-flags(riscv-plt) @spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
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PseudoRET
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...
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