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llvm-project/llvm/test/CodeGen
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Tomas Matheson fc712eb7aa [AArch64] Fix Copy Elemination for negative values 
Redundant Copy Elimination was eliminating a MOVi32imm -1 when it
determined that the value of the destination register is already -1.
However, it didn't take into account that the MOVi32imm zeroes the upper
32 bits (which are FFFFFFFF) and therefore cannot be eliminated.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D93100
 		2020-12-18 13:30:46 +00:00
..
AArch64 [AArch64] Fix Copy Elemination for negative values 2020-12-18 13:30:46 +00:00
AMDGPU Revert "Ensure SplitEdge to return the new block between the two given blocks" 2020-12-17 21:00:37 +00:00
ARC
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ARM Add intrinsics for saturating float to int casts 2020-12-18 11:09:41 +01:00
AVR [AVR] Optimize the 16-bit NEGW pseudo instruction 2020-11-17 17:51:58 +08:00
BPF [BPF] support atomic instructions 2020-12-03 07:38:00 -08:00
Generic [Debugify] Support checking Machine IR debug info 2020-12-16 22:17:25 -08:00
Hexagon [Hexagon] Rename test case, NFC 2020-12-15 19:05:31 -06:00
Inputs
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Lanai
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MIR [YAML] Use correct source location for unknown key errors. 2020-12-11 16:34:06 +00:00
MSP430 OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
Mips Revert "[FastISel] Flush local value map on ever instruction" and dependent patches 2020-12-01 14:26:23 -08:00
NVPTX OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
PowerPC [PowerPC] Select the D-Form load if we know its offset meets the requirement 2020-12-18 07:27:26 +00:00
RISCV [RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics. 2020-12-18 10:24:24 +08:00
SPARC OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
SystemZ [SystemZ] Improve handling of backchain offset. 2020-12-14 12:39:38 -06:00
Thumb OpaquePtr: Update more tests to use typed sret 2020-11-20 20:08:43 -05:00
Thumb2 [ARM] Match dual lane vmovs from insert_vector_elt 2020-12-15 15:58:52 +00:00
VE [VE] Support FRAMEADDR 2020-12-15 23:31:19 +09:00
WebAssembly [WebAssembly] Fix code generated for atomic operations in PIC mode 2020-12-08 18:41:32 -08:00
WinCFGuard [CFGuard] Add address-taken IAT tables and delay-load support 2020-11-17 18:24:45 -08:00
WinEH
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X86 [X86][AVX] Replace extract_subvector(broadcast(), 0) folds with generic SimplifyDemandedVectorEltsForTargetNode handling. 2020-12-18 11:51:10 +00:00
XCore Fix XCore test on Windows, the register order is reversed, for reasons unknown 2020-12-16 13:33:24 -08:00