llvm-project/llvm/lib/Target/SystemZ
Jonas Paulsson 77df2f2f38 [SystemZ] Adjust cost functions for subtargets that use LI + LOC instead of IPM
After recent improvements which makes better use of LOC instead of IPM, the
TTI cost functions also needs to be updated to reflect this.

This involves sext, zext and xor of i1.

The tests were updated so that for z13 the new costs are expected, while the
old costs are still checked for on zEC12.

Review: Ulrich Weigand
https://reviews.llvm.org/D51339

llvm-svn: 342207
2018-09-14 06:46:55 +00:00
..
AsmParser
Disassembler
InstPrinter
MCTargetDesc [MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixup 2018-06-06 09:40:06 +00:00
TargetInfo
CMakeLists.txt Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt 2018-04-23 12:49:34 +00:00
LLVMBuild.txt
README.txt
SystemZ.h [SystemZ] Handle SADDO et.al. and ADD/SUBCARRY 2018-04-30 17:54:28 +00:00
SystemZ.td [MachineOperand][Target] MachineOperand::isRenamable semantics changes 2018-02-23 18:25:08 +00:00
SystemZAsmPrinter.cpp [SystemZ] Support stackmaps and patchpoints 2018-03-02 20:39:30 +00:00
SystemZAsmPrinter.h [SystemZ] Support stackmaps and patchpoints 2018-03-02 20:39:30 +00:00
SystemZCallingConv.cpp
SystemZCallingConv.h
SystemZCallingConv.td [SystemZ] Add support for anyregcc calling convention 2018-03-02 20:40:11 +00:00
SystemZConstantPoolValue.cpp
SystemZConstantPoolValue.h
SystemZElimCompare.cpp [MI] Change the array of `MachineMemOperand` pointers to be 2018-08-16 21:30:05 +00:00
SystemZExpandPseudo.cpp Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
SystemZFeatures.td [SystemZ] Improve handling of Select pseudo-instructions 2018-04-30 15:49:27 +00:00
SystemZFrameLowering.cpp [SystemZ] Add support for anyregcc calling convention 2018-03-02 20:40:11 +00:00
SystemZFrameLowering.h [SystemZ] Fix common-code users of stack size 2018-03-02 20:38:41 +00:00
SystemZHazardRecognizer.cpp [SystemZ] Comment update. 2018-08-07 13:48:09 +00:00
SystemZHazardRecognizer.h [SystemZ] Improve decoding in case of instructions with four register operands. 2018-07-31 13:00:42 +00:00
SystemZISelDAGToDAG.cpp [SDAG] Remove the reliance on MI's allocation strategy for 2018-08-14 23:30:32 +00:00
SystemZISelLowering.cpp [MI] Change the array of `MachineMemOperand` pointers to be 2018-08-16 21:30:05 +00:00
SystemZISelLowering.h [SystemZ, TableGen] Fix shift count handling 2018-08-01 11:57:58 +00:00
SystemZInstrBuilder.h
SystemZInstrDFP.td
SystemZInstrFP.td [SystemZ] Replace subreg_r with subreg_h 2018-08-15 15:21:23 +00:00
SystemZInstrFormats.td [SystemZ] Bugfix for MVCLoop CC clobbering. 2018-05-07 10:48:43 +00:00
SystemZInstrHFP.td
SystemZInstrInfo.cpp [SystemZ] Replace subreg_r with subreg_h 2018-08-15 15:21:23 +00:00
SystemZInstrInfo.h
SystemZInstrInfo.td [SystemZ, TableGen] Fix shift count handling 2018-08-01 11:57:58 +00:00
SystemZInstrSystem.td
SystemZInstrVector.td [SystemZ] Replace subreg_r with subreg_h 2018-08-15 15:21:23 +00:00
SystemZLDCleanup.cpp
SystemZLongBranch.cpp [DebugInfo] Examine all uses of isDebugValue() for debug instructions. 2018-05-09 02:42:00 +00:00
SystemZMCInstLower.cpp
SystemZMCInstLower.h
SystemZMachineFunctionInfo.cpp
SystemZMachineFunctionInfo.h
SystemZMachineScheduler.cpp [SystemZ] Improve decoding in case of instructions with four register operands. 2018-07-31 13:00:42 +00:00
SystemZMachineScheduler.h Remove trailing space 2018-07-30 19:41:25 +00:00
SystemZOperands.td [SystemZ, TableGen] Fix shift count handling 2018-08-01 11:57:58 +00:00
SystemZOperators.td [SelectionDAG][X86][SystemZ] Add a generic nonvolatile_store/nonvolatile_load pattern fragment in TargetSelectionDAG.td 2018-08-07 17:34:59 +00:00
SystemZPatterns.td
SystemZProcessors.td
SystemZRegisterInfo.cpp [SystemZ] Do not use glue to represent condition code dependencies 2018-04-30 17:52:32 +00:00
SystemZRegisterInfo.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
SystemZRegisterInfo.td [SystemZ] Replace subreg_r with subreg_h 2018-08-15 15:21:23 +00:00
SystemZSchedule.td [SystemZ] Improve handling of instructions which expand to several groups 2018-08-03 10:43:05 +00:00
SystemZScheduleZ13.td [SystemZ] Improve handling of instructions which expand to several groups 2018-08-03 10:43:05 +00:00
SystemZScheduleZ14.td [SystemZ] Improve handling of instructions which expand to several groups 2018-08-03 10:43:05 +00:00
SystemZScheduleZ196.td [SystemZ] Improve handling of instructions which expand to several groups 2018-08-03 10:43:05 +00:00
SystemZScheduleZEC12.td [SystemZ] Improve handling of instructions which expand to several groups 2018-08-03 10:43:05 +00:00
SystemZSelectionDAGInfo.cpp [SystemZ] Do not use glue to represent condition code dependencies 2018-04-30 17:52:32 +00:00
SystemZSelectionDAGInfo.h
SystemZShortenInst.cpp
SystemZSubtarget.cpp [SystemZ] New CL option to enable subreg liveness 2018-08-15 15:04:49 +00:00
SystemZSubtarget.h [SystemZ] New CL option to enable subreg liveness 2018-08-15 15:04:49 +00:00
SystemZTDC.cpp
SystemZTargetMachine.cpp Move TargetLoweringObjectFile from CodeGen to Target to fix layering 2018-03-23 23:58:19 +00:00
SystemZTargetMachine.h
SystemZTargetTransformInfo.cpp [SystemZ] Adjust cost functions for subtargets that use LI + LOC instead of IPM 2018-09-14 06:46:55 +00:00
SystemZTargetTransformInfo.h [SystemZ] Increase the amount of inlining. 2018-08-13 13:31:30 +00:00

README.txt

//===---------------------------------------------------------------------===//
// Random notes about and ideas for the SystemZ backend.
//===---------------------------------------------------------------------===//

The initial backend is deliberately restricted to z10.  We should add support
for later architectures at some point.

--

If an inline asm ties an i32 "r" result to an i64 input, the input
will be treated as an i32, leaving the upper bits uninitialised.
For example:

define void @f4(i32 *%dst) {
  %val = call i32 asm "blah $0", "=r,0" (i64 103)
  store i32 %val, i32 *%dst
  ret void
}

from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
to load 103.  This seems to be a general target-independent problem.

--

The tuning of the choice between LOAD ADDRESS (LA) and addition in
SystemZISelDAGToDAG.cpp is suspect.  It should be tweaked based on
performance measurements.

--

There is no scheduling support.

--

We don't use the BRANCH ON INDEX instructions.

--

We only use MVC, XC and CLC for constant-length block operations.
We could extend them to variable-length operations too,
using EXECUTE RELATIVE LONG.

MVCIN, MVCLE and CLCLE may be worthwhile too.

--

We don't use CUSE or the TRANSLATE family of instructions for string
operations.  The TRANSLATE ones are probably more difficult to exploit.

--

We don't take full advantage of builtins like fabsl because the calling
conventions require f128s to be returned by invisible reference.

--

ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
produce a carry.  SUBTRACT LOGICAL IMMEDIATE could be useful when we
need to produce a borrow.  (Note that there are no memory forms of
ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
part of 128-bit memory operations would probably need to be done
via a register.)

--

We don't use ICM, STCM, or CLM.

--

We don't use ADD (LOGICAL) HIGH, SUBTRACT (LOGICAL) HIGH,
or COMPARE (LOGICAL) HIGH yet.

--

DAGCombiner doesn't yet fold truncations of extended loads.  Functions like:

    unsigned long f (unsigned long x, unsigned short *y)
    {
      return (x << 32) | *y;
    }

therefore end up as:

        sllg    %r2, %r2, 32
        llgh    %r0, 0(%r3)
        lr      %r2, %r0
        br      %r14

but truncating the load would give:

        sllg    %r2, %r2, 32
        lh      %r2, 0(%r3)
        br      %r14

--

Functions like:

define i64 @f1(i64 %a) {
  %and = and i64 %a, 1
  ret i64 %and
}

ought to be implemented as:

        lhi     %r0, 1
        ngr     %r2, %r0
        br      %r14

but two-address optimizations reverse the order of the AND and force:

        lhi     %r0, 1
        ngr     %r0, %r2
        lgr     %r2, %r0
        br      %r14

CodeGen/SystemZ/and-04.ll has several examples of this.

--

Out-of-range displacements are usually handled by loading the full
address into a register.  In many cases it would be better to create
an anchor point instead.  E.g. for:

define void @f4a(i128 *%aptr, i64 %base) {
  %addr = add i64 %base, 524288
  %bptr = inttoptr i64 %addr to i128 *
  %a = load volatile i128 *%aptr
  %b = load i128 *%bptr
  %add = add i128 %a, %b
  store i128 %add, i128 *%aptr
  ret void
}

(from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
into separate registers, rather than using %base+524288 as a base for both.

--

Dynamic stack allocations round the size to 8 bytes and then allocate
that rounded amount.  It would be simpler to subtract the unrounded
size from the copy of the stack pointer and then align the result.
See CodeGen/SystemZ/alloca-01.ll for an example.

--

If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.

--

We might want to model all access registers and use them to spill
32-bit values.

--

We might want to use the 'overflow' condition of eg. AR to support
llvm.sadd.with.overflow.i32 and related instructions - the generated code
for signed overflow check is currently quite bad.  This would improve
the results of using -ftrapv.