forked from OSchip/llvm-project
138 lines
4.3 KiB
LLVM
138 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; CTPOP
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;
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define <vscale x 16 x i1> @ctpop_nxv16i1(<vscale x 16 x i1> %a) {
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; CHECK-LABEL: ctpop_nxv16i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i1> @llvm.ctpop.nxv16i1(<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %res
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}
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define <vscale x 8 x i1> @ctpop_nxv8i1(<vscale x 8 x i1> %a) {
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; CHECK-LABEL: ctpop_nxv8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i1> @llvm.ctpop.nxv8i1(<vscale x 8 x i1> %a)
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ret <vscale x 8 x i1> %res
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}
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define <vscale x 4 x i1> @ctpop_nxv4i1(<vscale x 4 x i1> %a) {
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; CHECK-LABEL: ctpop_nxv4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i1> @llvm.ctpop.nxv4i1(<vscale x 4 x i1> %a)
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ret <vscale x 4 x i1> %res
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}
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define <vscale x 2 x i1> @ctpop_nxv2i1(<vscale x 2 x i1> %a) {
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; CHECK-LABEL: ctpop_nxv2i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i1> @llvm.ctpop.nxv2i1(<vscale x 2 x i1> %a)
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ret <vscale x 2 x i1> %res
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}
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; CTLZ
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define <vscale x 16 x i1> @ctlz_nxv16i1(<vscale x 16 x i1> %a) {
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; CHECK-LABEL: ctlz_nxv16i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.b
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i1> @llvm.ctlz.nxv16i1(<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %res
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}
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define <vscale x 8 x i1> @ctlz_nxv8i1(<vscale x 8 x i1> %a) {
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; CHECK-LABEL: ctlz_nxv8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i1> @llvm.ctlz.nxv8i1(<vscale x 8 x i1> %a)
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ret <vscale x 8 x i1> %res
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}
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define <vscale x 4 x i1> @ctlz_nxv4i1(<vscale x 4 x i1> %a) {
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; CHECK-LABEL: ctlz_nxv4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i1> @llvm.ctlz.nxv4i1(<vscale x 4 x i1> %a)
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ret <vscale x 4 x i1> %res
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}
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define <vscale x 2 x i1> @ctlz_nxv2i1(<vscale x 2 x i1> %a) {
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; CHECK-LABEL: ctlz_nxv2i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i1> @llvm.ctlz.nxv2i1(<vscale x 2 x i1> %a)
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ret <vscale x 2 x i1> %res
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}
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; CTTZ
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define <vscale x 16 x i1> @cttz_nxv16i1(<vscale x 16 x i1> %a) {
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; CHECK-LABEL: cttz_nxv16i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.b
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i1> @llvm.cttz.nxv16i1(<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %res
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}
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define <vscale x 8 x i1> @cttz_nxv8i1(<vscale x 8 x i1> %a) {
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; CHECK-LABEL: cttz_nxv8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i1> @llvm.cttz.nxv8i1(<vscale x 8 x i1> %a)
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ret <vscale x 8 x i1> %res
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}
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define <vscale x 4 x i1> @cttz_nxv4i1(<vscale x 4 x i1> %a) {
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; CHECK-LABEL: cttz_nxv4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i1> @llvm.cttz.nxv4i1(<vscale x 4 x i1> %a)
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ret <vscale x 4 x i1> %res
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}
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define <vscale x 2 x i1> @cttz_nxv2i1(<vscale x 2 x i1> %a) {
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; CHECK-LABEL: cttz_nxv2i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i1> @llvm.cttz.nxv2i1(<vscale x 2 x i1> %a)
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ret <vscale x 2 x i1> %res
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}
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declare <vscale x 16 x i1> @llvm.ctpop.nxv16i1(<vscale x 16 x i1>)
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declare <vscale x 8 x i1> @llvm.ctpop.nxv8i1(<vscale x 8 x i1>)
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declare <vscale x 4 x i1> @llvm.ctpop.nxv4i1(<vscale x 4 x i1>)
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declare <vscale x 2 x i1> @llvm.ctpop.nxv2i1(<vscale x 2 x i1>)
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declare <vscale x 16 x i1> @llvm.ctlz.nxv16i1(<vscale x 16 x i1>)
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declare <vscale x 8 x i1> @llvm.ctlz.nxv8i1(<vscale x 8 x i1>)
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declare <vscale x 4 x i1> @llvm.ctlz.nxv4i1(<vscale x 4 x i1>)
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declare <vscale x 2 x i1> @llvm.ctlz.nxv2i1(<vscale x 2 x i1>)
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declare <vscale x 16 x i1> @llvm.cttz.nxv16i1(<vscale x 16 x i1>)
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declare <vscale x 8 x i1> @llvm.cttz.nxv8i1(<vscale x 8 x i1>)
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declare <vscale x 4 x i1> @llvm.cttz.nxv4i1(<vscale x 4 x i1>)
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declare <vscale x 2 x i1> @llvm.cttz.nxv2i1(<vscale x 2 x i1>)
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