forked from OSchip/llvm-project
269 lines
7.0 KiB
LLVM
269 lines
7.0 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK
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; Test efficient codegen of vector extends up from legal type to 128 bit
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; and 256 bit vector types.
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;-----
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; Vectors of i16.
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;-----
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; FALLBACK-NOT: remark:{{.*}}(in function: func1)
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define <8 x i16> @func1(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: func1:
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; CHECK-NEXT: ushll.8h v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <8 x i8> %v0 to <8 x i16>
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ret <8 x i16> %r
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}
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; FALLBACK-NOT: remark:{{.*}}(in function: func2)
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define <8 x i16> @func2(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: func2:
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; CHECK-NEXT: sshll.8h v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <8 x i8> %v0 to <8 x i16>
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ret <8 x i16> %r
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}
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define <16 x i16> @func3(<16 x i8> %v0) nounwind {
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; CHECK-LABEL: func3:
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; CHECK-NEXT: ushll2.8h v1, v0, #0
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; CHECK-NEXT: ushll.8h v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <16 x i8> %v0 to <16 x i16>
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ret <16 x i16> %r
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}
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define <16 x i16> @func4(<16 x i8> %v0) nounwind {
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; CHECK-LABEL: func4:
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; CHECK-NEXT: sshll2.8h v1, v0, #0
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; CHECK-NEXT: sshll.8h v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <16 x i8> %v0 to <16 x i16>
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ret <16 x i16> %r
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}
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;-----
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; Vectors of i32.
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;-----
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; FALLBACK-NOT: remark:{{.*}}(in function: afunc1)
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define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
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; CHECK-LABEL: afunc1:
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <4 x i16> %v0 to <4 x i32>
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ret <4 x i32> %r
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}
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; FALLBACK-NOT: remark:{{.*}}(in function: afunc2)
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define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
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; CHECK-LABEL: afunc2:
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <4 x i16> %v0 to <4 x i32>
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ret <4 x i32> %r
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}
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define <8 x i32> @afunc3(<8 x i16> %v0) nounwind {
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; CHECK-LABEL: afunc3:
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; CHECK-NEXT: ushll2.4s v1, v0, #0
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <8 x i16> %v0 to <8 x i32>
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ret <8 x i32> %r
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}
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define <8 x i32> @afunc4(<8 x i16> %v0) nounwind {
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; CHECK-LABEL: afunc4:
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; CHECK-NEXT: sshll2.4s v1, v0, #0
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <8 x i16> %v0 to <8 x i32>
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ret <8 x i32> %r
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}
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define <8 x i32> @bfunc1(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: bfunc1:
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; CHECK-NEXT: ushll.8h v0, v0, #0
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; CHECK-NEXT: ushll2.4s v1, v0, #0
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <8 x i8> %v0 to <8 x i32>
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ret <8 x i32> %r
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}
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define <8 x i32> @bfunc2(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: bfunc2:
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; CHECK-NEXT: sshll.8h v0, v0, #0
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; CHECK-NEXT: sshll2.4s v1, v0, #0
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <8 x i8> %v0 to <8 x i32>
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ret <8 x i32> %r
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}
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;-----
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; Vectors of i64.
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;-----
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define <4 x i64> @zfunc1(<4 x i32> %v0) nounwind {
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; CHECK-LABEL: zfunc1:
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; CHECK-NEXT: ushll2.2d v1, v0, #0
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; CHECK-NEXT: ushll.2d v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <4 x i32> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @zfunc2(<4 x i32> %v0) nounwind {
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; CHECK-LABEL: zfunc2:
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; CHECK-NEXT: sshll2.2d v1, v0, #0
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; CHECK-NEXT: sshll.2d v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <4 x i32> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @bfunc3(<4 x i16> %v0) nounwind {
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; CHECK-LABEL: func3:
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ushll2.2d v1, v0, #0
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; CHECK-NEXT: ushll.2d v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <4 x i16> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @cfunc4(<4 x i16> %v0) nounwind {
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; CHECK-LABEL: func4:
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: sshll2.2d v1, v0, #0
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; CHECK-NEXT: sshll.2d v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <4 x i16> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @zext_v4i8_to_v4i64(<4 x i8> %v0) nounwind {
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; CHECK-LABEL: zext_v4i8_to_v4i64:
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; CHECK-NEXT: bic.4h v0, #255, lsl #8
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ushll2.2d v1, v0, #0
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; CHECK-NEXT: ushll.2d v0, v0, #0
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; CHECK-NEXT: ret
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;
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%r = zext <4 x i8> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @sext_v4i8_to_v4i64(<4 x i8> %v0) nounwind {
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; CHECK-LABEL: sext_v4i8_to_v4i64:
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ushll.2d v1, v0, #0
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; CHECK-NEXT: ushll2.2d v0, v0, #0
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; CHECK-NEXT: shl.2d v0, v0, #56
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; CHECK-NEXT: shl.2d v2, v1, #56
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; CHECK-NEXT: sshr.2d v1, v0, #56
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; CHECK-NEXT: sshr.2d v0, v2, #56
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; CHECK-NEXT: ret
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;
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%r = sext <4 x i8> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <8 x i64> @zext_v8i8_to_v8i64(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: zext_v8i8_to_v8i64:
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; CHECK-NEXT: ushll.8h v0, v0, #0
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; CHECK-NEXT: ushll2.4s v2, v0, #0
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ushll2.2d v3, v2, #0
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; CHECK-NEXT: ushll2.2d v1, v0, #0
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; CHECK-NEXT: ushll.2d v2, v2, #0
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; CHECK-NEXT: ushll.2d v0, v0, #0
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; CHECK-NEXT: ret
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;
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%r = zext <8 x i8> %v0 to <8 x i64>
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ret <8 x i64> %r
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}
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define <8 x i64> @sext_v8i8_to_v8i64(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: sext_v8i8_to_v8i64:
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; CHECK-NEXT: sshll.8h v0, v0, #0
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; CHECK-NEXT: sshll2.4s v2, v0, #0
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: sshll2.2d v3, v2, #0
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; CHECK-NEXT: sshll2.2d v1, v0, #0
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; CHECK-NEXT: sshll.2d v2, v2, #0
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; CHECK-NEXT: sshll.2d v0, v0, #0
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; CHECK-NEXT: ret
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;
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%r = sext <8 x i8> %v0 to <8 x i64>
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ret <8 x i64> %r
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}
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; Extends of vectors of i1.
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define <32 x i8> @zext_v32i1(<32 x i1> %arg) {
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; CHECK-LABEL: zext_v32i1:
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; CHECK: and.16b v0, v0, v2
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; CHECK-NEXT: and.16b v1, v1, v2
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; CHECK-NEXT: ret
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%res = zext <32 x i1> %arg to <32 x i8>
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ret <32 x i8> %res
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}
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define <32 x i8> @sext_v32i1(<32 x i1> %arg) {
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; CHECK-LABEL: sext_v32i1:
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; CHECK: shl.16b v0, v0, #7
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; CHECK-NEXT: shl.16b v1, v1, #7
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; CHECK-NEXT: sshr.16b v0, v0, #7
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; CHECK-NEXT: sshr.16b v1, v1, #7
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; CHECK-NEXT: ret
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;
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%res = sext <32 x i1> %arg to <32 x i8>
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ret <32 x i8> %res
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}
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define <64 x i8> @zext_v64i1(<64 x i1> %arg) {
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; CHECK-LABEL: zext_v64i1:
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; CHECK: and.16b v0, v0, [[V4:v.+]]
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; CHECK-NEXT: and.16b v1, v1, [[V4]]
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; CHECK-NEXT: and.16b v2, v2, [[V4]]
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; CHECK-NEXT: and.16b v3, v3, [[V4]]
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; CHECK-NEXT: ret
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;
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%res = zext <64 x i1> %arg to <64 x i8>
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ret <64 x i8> %res
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}
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define <64 x i8> @sext_v64i1(<64 x i1> %arg) {
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; CHECK-LABEL: sext_v64i1:
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; CHECK: shl.16b v0, v0, #7
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; CHECK-NEXT: shl.16b v3, v3, #7
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; CHECK-NEXT: shl.16b v2, v2, #7
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; CHECK-NEXT: shl.16b [[V4:v.+]], v1, #7
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; CHECK-NEXT: sshr.16b v0, v0, #7
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; CHECK-NEXT: sshr.16b v1, v3, #7
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; CHECK-NEXT: sshr.16b v2, v2, #7
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; CHECK-NEXT: sshr.16b v3, [[V4]], #7
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; CHECK-NEXT: ret
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;
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%res = sext <64 x i1> %arg to <64 x i8>
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ret <64 x i8> %res
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}
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define <1 x i128> @sext_v1x64(<1 x i64> %arg) {
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; CHECK-LABEL: sext_v1x64:
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; CHECK-NEXT: .cfi_startproc
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: asr x1, x8, #63
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; CHECK-NEXT: mov.d v0[1], x1
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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;
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%res = sext <1 x i64> %arg to <1 x i128>
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ret <1 x i128> %res
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}
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