forked from OSchip/llvm-project
45 lines
1.3 KiB
LLVM
45 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
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define i64 @addc_adde(i64 %a, i64 %b) {
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; RV32I-LABEL: addc_adde:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: add a1, a1, a3
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; RV32I-NEXT: add a2, a0, a2
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: add a1, a1, a0
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = add i64 %a, %b
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ret i64 %1
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}
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define i64 @subc_sube(i64 %a, i64 %b) {
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; RV32I-LABEL: subc_sube:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: sltu a3, a0, a2
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: sub a0, a0, a2
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = sub i64 %a, %b
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ret i64 %1
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}
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