forked from OSchip/llvm-project
222 lines
8.6 KiB
LLVM
222 lines
8.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \
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; RUN: -target-abi ilp32f < %s \
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; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+d \
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; RUN: -target-abi ilp32d < %s \
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; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s
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; This file contains tests that should have identical output for the ilp32f
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; and ilp32d ABIs.
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define i32 @callee_float_in_fpr(i32 %a, float %b) nounwind {
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; RV32-ILP32FD-LABEL: callee_float_in_fpr:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
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; RV32-ILP32FD-NEXT: add a0, a0, a1
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; RV32-ILP32FD-NEXT: ret
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%b_fptosi = fptosi float %b to i32
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%1 = add i32 %a, %b_fptosi
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ret i32 %1
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}
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define i32 @caller_float_in_fpr() nounwind {
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; RV32-ILP32FD-LABEL: caller_float_in_fpr:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: addi sp, sp, -16
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; RV32-ILP32FD-NEXT: sw ra, 12(sp)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI1_0)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI1_0)
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; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
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; RV32-ILP32FD-NEXT: addi a0, zero, 1
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; RV32-ILP32FD-NEXT: call callee_float_in_fpr
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; RV32-ILP32FD-NEXT: lw ra, 12(sp)
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; RV32-ILP32FD-NEXT: addi sp, sp, 16
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; RV32-ILP32FD-NEXT: ret
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%1 = call i32 @callee_float_in_fpr(i32 1, float 2.0)
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ret i32 %1
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}
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; Must keep define on a single line due to an update_llc_test_checks.py limitation
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define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, float %f) nounwind {
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; RV32-ILP32FD-LABEL: callee_float_in_fpr_exhausted_gprs:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: lw a0, 0(sp)
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; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
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; RV32-ILP32FD-NEXT: add a0, a0, a1
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; RV32-ILP32FD-NEXT: ret
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%f_fptosi = fptosi float %f to i32
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%1 = add i32 %e, %f_fptosi
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ret i32 %1
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}
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define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
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; RV32-ILP32FD-LABEL: caller_float_in_fpr_exhausted_gprs:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: addi sp, sp, -16
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; RV32-ILP32FD-NEXT: sw ra, 12(sp)
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; RV32-ILP32FD-NEXT: addi a1, zero, 5
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI3_0)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI3_0)
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; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
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; RV32-ILP32FD-NEXT: addi a0, zero, 1
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; RV32-ILP32FD-NEXT: addi a2, zero, 2
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; RV32-ILP32FD-NEXT: addi a4, zero, 3
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; RV32-ILP32FD-NEXT: addi a6, zero, 4
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; RV32-ILP32FD-NEXT: sw a1, 0(sp)
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; RV32-ILP32FD-NEXT: mv a1, zero
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; RV32-ILP32FD-NEXT: mv a3, zero
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; RV32-ILP32FD-NEXT: mv a5, zero
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; RV32-ILP32FD-NEXT: mv a7, zero
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; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs
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; RV32-ILP32FD-NEXT: lw ra, 12(sp)
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; RV32-ILP32FD-NEXT: addi sp, sp, 16
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; RV32-ILP32FD-NEXT: ret
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%1 = call i32 @callee_float_in_fpr_exhausted_gprs(
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i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0)
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ret i32 %1
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}
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; Must keep define on a single line due to an update_llc_test_checks.py limitation
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define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind {
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; RV32-ILP32FD-LABEL: callee_float_in_gpr_exhausted_fprs:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: fmv.w.x ft0, a0
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; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa7, rtz
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; RV32-ILP32FD-NEXT: fcvt.w.s a1, ft0, rtz
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; RV32-ILP32FD-NEXT: add a0, a0, a1
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; RV32-ILP32FD-NEXT: ret
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%h_fptosi = fptosi float %h to i32
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%i_fptosi = fptosi float %i to i32
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%1 = add i32 %h_fptosi, %i_fptosi
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ret i32 %1
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}
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define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
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; RV32-ILP32FD-LABEL: caller_float_in_gpr_exhausted_fprs:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: addi sp, sp, -16
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; RV32-ILP32FD-NEXT: sw ra, 12(sp)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_0)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_0)
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; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_1)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_1)
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; RV32-ILP32FD-NEXT: flw fa1, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_2)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_2)
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; RV32-ILP32FD-NEXT: flw fa2, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_3)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_3)
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; RV32-ILP32FD-NEXT: flw fa3, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_4)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_4)
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; RV32-ILP32FD-NEXT: flw fa4, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_5)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_5)
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; RV32-ILP32FD-NEXT: flw fa5, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_6)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_6)
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; RV32-ILP32FD-NEXT: flw fa6, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_7)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_7)
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; RV32-ILP32FD-NEXT: flw fa7, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, 266496
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; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs
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; RV32-ILP32FD-NEXT: lw ra, 12(sp)
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; RV32-ILP32FD-NEXT: addi sp, sp, 16
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; RV32-ILP32FD-NEXT: ret
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%1 = call i32 @callee_float_in_gpr_exhausted_fprs(
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float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0,
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float 7.0, float 8.0, float 9.0)
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ret i32 %1
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}
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; Must keep define on a single line due to an update_llc_test_checks.py limitation
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define i32 @callee_float_on_stack_exhausted_gprs_fprs(i64 %a, float %b, i64 %c, float %d, i64 %e, float %f, i64 %g, float %h, float %i, float %j, float %k, float %l, float %m) nounwind {
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; RV32-ILP32FD-LABEL: callee_float_on_stack_exhausted_gprs_fprs:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: flw ft0, 0(sp)
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; RV32-ILP32FD-NEXT: fcvt.w.s a0, ft0, rtz
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; RV32-ILP32FD-NEXT: add a0, a6, a0
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; RV32-ILP32FD-NEXT: ret
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%g_trunc = trunc i64 %g to i32
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%m_fptosi = fptosi float %m to i32
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%1 = add i32 %g_trunc, %m_fptosi
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ret i32 %1
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}
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define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
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; RV32-ILP32FD-LABEL: caller_float_on_stack_exhausted_gprs_fprs:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: addi sp, sp, -16
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; RV32-ILP32FD-NEXT: sw ra, 12(sp)
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; RV32-ILP32FD-NEXT: lui a1, 267520
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_0)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_0)
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; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_1)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_1)
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; RV32-ILP32FD-NEXT: flw fa1, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_2)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_2)
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; RV32-ILP32FD-NEXT: flw fa2, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_3)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_3)
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; RV32-ILP32FD-NEXT: flw fa3, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_4)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_4)
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; RV32-ILP32FD-NEXT: flw fa4, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_5)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_5)
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; RV32-ILP32FD-NEXT: flw fa5, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_6)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_6)
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; RV32-ILP32FD-NEXT: flw fa6, 0(a0)
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_7)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_7)
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; RV32-ILP32FD-NEXT: flw fa7, 0(a0)
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; RV32-ILP32FD-NEXT: addi a0, zero, 1
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; RV32-ILP32FD-NEXT: addi a2, zero, 3
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; RV32-ILP32FD-NEXT: addi a4, zero, 5
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; RV32-ILP32FD-NEXT: addi a6, zero, 7
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; RV32-ILP32FD-NEXT: sw a1, 0(sp)
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; RV32-ILP32FD-NEXT: mv a1, zero
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; RV32-ILP32FD-NEXT: mv a3, zero
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; RV32-ILP32FD-NEXT: mv a5, zero
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; RV32-ILP32FD-NEXT: mv a7, zero
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; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs
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; RV32-ILP32FD-NEXT: lw ra, 12(sp)
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; RV32-ILP32FD-NEXT: addi sp, sp, 16
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; RV32-ILP32FD-NEXT: ret
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%1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs(
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i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0,
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float 9.0, float 10.0, float 11.0, float 12.0, float 13.0)
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ret i32 %1
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}
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define float @callee_float_ret() nounwind {
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; RV32-ILP32FD-LABEL: callee_float_ret:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI8_0)
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; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI8_0)
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; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
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; RV32-ILP32FD-NEXT: ret
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ret float 1.0
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}
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define i32 @caller_float_ret() nounwind {
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; RV32-ILP32FD-LABEL: caller_float_ret:
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; RV32-ILP32FD: # %bb.0:
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; RV32-ILP32FD-NEXT: addi sp, sp, -16
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; RV32-ILP32FD-NEXT: sw ra, 12(sp)
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; RV32-ILP32FD-NEXT: call callee_float_ret
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; RV32-ILP32FD-NEXT: fmv.x.w a0, fa0
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; RV32-ILP32FD-NEXT: lw ra, 12(sp)
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; RV32-ILP32FD-NEXT: addi sp, sp, 16
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; RV32-ILP32FD-NEXT: ret
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%1 = call float @callee_float_ret()
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%2 = bitcast float %1 to i32
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ret i32 %2
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}
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