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llvm-project/llvm/test/CodeGen/MIR
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Yuanfang Chen 4ad7685258 Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 
This reverts commit 80a34ae311 with fixes.

Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on
MachineVerifierPass by default on X86 and the fact that
inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll
are not expected to generate functioning machine code, this would go
down to `report_fatal_error` in MachineVerifierPass. Here passing
`-verify-machineinstrs=0` to make the intent explicit.
 		2020-02-13 10:16:06 -08:00
..
AArch64 [MIRNamer]: Make the check lines in the test robust with regex. 2019-11-16 22:58:45 -08:00
AMDGPU AMDGPU: Split denormal mode tracking bits 2020-02-04 10:44:21 -08:00
ARM [ARM][Thumb2] Fix ADD/SUB invalid writes to SP 2020-01-14 11:47:19 +00:00
Generic [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands. 2019-12-16 18:25:04 -05:00
Hexagon Revert "[DebugInfo] Enable the debug entry values feature by default" 2020-02-12 11:59:04 +01:00
Mips [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
NVPTX
…
PowerPC [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 2019-09-13 14:18:36 +00:00
WebAssembly [WebAssembly] Fix tests missed in rL374235 2019-10-09 23:06:38 +00:00
X86 Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.