forked from OSchip/llvm-project
77 lines
2.2 KiB
LLVM
77 lines
2.2 KiB
LLVM
; RUN: llc -march=hexagon -machine-sink-split < %s
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; REQUIRES: asserts
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; MachineSink should not sink an MI which is used in a non-phi instruction
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; in an MBB with multiple predecessors.
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target triple = "hexagon-unknown--elf"
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; Function Attrs: nounwind
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define void @f0() #0 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b0
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unreachable
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b2: ; preds = %b0
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%v0 = load i8*, i8** undef, align 4
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%v1 = getelementptr inbounds i8, i8* %v0, i32 1
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%v2 = load i8, i8* %v0, align 1, !tbaa !0
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%v3 = zext i8 %v2 to i32
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%v4 = shl nuw nsw i32 %v3, 8
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br i1 undef, label %b3, label %b5
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b3: ; preds = %b2
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br i1 undef, label %b15, label %b4
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b4: ; preds = %b3
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br label %b5
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b5: ; preds = %b4, %b2
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%v5 = phi i8* [ undef, %b4 ], [ %v1, %b2 ]
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%v6 = load i8, i8* %v5, align 1, !tbaa !0
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%v7 = zext i8 %v6 to i32
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%v8 = add nsw i32 %v7, %v4
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%v9 = add nsw i32 %v8, -2
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br label %b6
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b6: ; preds = %b8, %b5
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br i1 false, label %b7, label %b8
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b7: ; preds = %b6
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unreachable
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b8: ; preds = %b6
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br i1 undef, label %b6, label %b9
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b9: ; preds = %b8
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br i1 undef, label %b10, label %b14
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b10: ; preds = %b9
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br i1 undef, label %b11, label %b13
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b11: ; preds = %b10
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br i1 undef, label %b12, label %b13
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b12: ; preds = %b11
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unreachable
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b13: ; preds = %b11, %b10
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store i32 %v9, i32* undef, align 4, !tbaa !3
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unreachable
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b14: ; preds = %b9
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unreachable
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b15: ; preds = %b3
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ret void
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}
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attributes #0 = { nounwind }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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!3 = !{!4, !4, i64 0}
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!4 = !{!"int", !1, i64 0}
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