forked from OSchip/llvm-project
205 lines
5.6 KiB
YAML
205 lines
5.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
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---
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name: fadd_s32_vvv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_FADD %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fadd_s32_vsv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX6-LABEL: name: fadd_s32_vsv
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; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_FADD %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fadd_s32_vvs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX6-LABEL: name: fadd_s32_vvs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_FADD %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fadd_s32_vvv_fabs_lhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_FABS %0
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%3:vgpr(s32) = G_FADD %2, %1
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S_ENDPGM 0, implicit %3
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...
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---
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name: fadd_s32_vvv_fabs_rhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_FABS %1
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%3:vgpr(s32) = G_FADD %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: fadd_s32_vvv_fneg_fabs_lhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_FABS %0
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%3:vgpr(s32) = G_FNEG %2
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%4:vgpr(s32) = G_FADD %3, %1
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S_ENDPGM 0, implicit %4
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...
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---
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name: fadd_s32_vvv_fneg_fabs_rhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_FABS %1
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%3:vgpr(s32) = G_FNEG %2
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%4:vgpr(s32) = G_FADD %1, %3
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S_ENDPGM 0, implicit %4
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...
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# Need to look through reg bank copy to find source modifiers
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---
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name: fadd_s32_fneg_copy_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:sgpr(s32) = G_FNEG %1
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%3:vgpr(s32) = COPY %2
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%4:vgpr(s32) = G_FADD %0, %3
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S_ENDPGM 0, implicit %4
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...
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# Need to look through copy in between fneg and fabs
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---
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name: fadd_s32_copy_fneg_copy_fabs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:sgpr(s32) = G_FABS %1
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%3:sgpr(s32) = COPY %2
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%4:sgpr(s32) = G_FNEG %3
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%5:sgpr(s32) = COPY %4
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%6:vgpr(s32) = G_FADD %0, %5
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S_ENDPGM 0, implicit %6
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...
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