forked from OSchip/llvm-project
22 lines
1.0 KiB
TableGen
22 lines
1.0 KiB
TableGen
//==- HexagonInstrFormatsV60.td - Hexagon Instruction Formats -*- tablegen -==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V60 instruction classes in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//----------------------------------------------------------------------------//
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// Instruction Classes Definitions +
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//----------------------------------------------------------------------------//
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class CVI_VA_Resource<dag outs, dag ins, string asmstr,
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list<dag> pattern = [], string cstr = "",
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InstrItinClass itin = CVI_VA>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
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OpcodeHexagon, Requires<[HasV60, UseHVX]>;
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