| .. |
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AsmParser
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[AMDGPU][MC] Corrected MTBUF parsing and decoding
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2020-07-15 19:46:00 +03:00 |
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Disassembler
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[AMDGPU] Add gfx1030 target
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2020-06-15 16:18:05 -07:00 |
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MCTargetDesc
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[AMDGPU][MC] Corrected MTBUF parsing and decoding
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2020-07-15 19:46:00 +03:00 |
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TargetInfo
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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Utils
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[AMDGPU][MC] Corrected MTBUF parsing and decoding
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2020-07-15 19:46:00 +03:00 |
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AMDGPU.h
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AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
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2020-05-31 20:40:14 -04:00 |
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AMDGPU.td
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[AMDGPU] Add gfx1030 target
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2020-06-15 16:18:05 -07:00 |
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AMDGPUAliasAnalysis.cpp
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AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory
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2020-05-09 16:00:08 -04:00 |
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AMDGPUAliasAnalysis.h
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Remove orphan AMDGPUAAResult::Aliases and AMDGPUAAResult::PathAliases declarations. NFC.
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2020-06-25 16:00:44 +01:00 |
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AMDGPUAlwaysInlinePass.cpp
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AMDGPU: Hack out noinline on functions using LDS globals
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2020-04-02 14:12:07 -04:00 |
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPU: Annotate functions that have stack objects
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2020-05-19 18:51:00 -04:00 |
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AMDGPUAnnotateUniformValues.cpp
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AMDGPU: Fix not using scalar loads for global reads in shaders
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2020-06-02 09:49:23 -04:00 |
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AMDGPUArgumentUsageInfo.cpp
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AMDGPU/GlobalISel: Add types to special inputs
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2020-07-06 17:00:55 -04:00 |
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AMDGPUArgumentUsageInfo.h
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AMDGPU/GlobalISel: Add types to special inputs
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2020-07-06 17:00:55 -04:00 |
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AMDGPUAsmPrinter.cpp
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[AMDGPU][CODEGEN] Added support of new inline assembler constraints
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2020-07-02 17:20:15 +03:00 |
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AMDGPUAsmPrinter.h
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[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
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2020-02-13 22:08:55 -08:00 |
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AMDGPUAtomicOptimizer.cpp
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[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
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2020-05-29 17:54:17 -07:00 |
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AMDGPUCallLowering.cpp
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GlobalISel: Handle EVT argument lowering correctly
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2020-07-07 16:36:14 -04:00 |
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AMDGPUCallLowering.h
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[Alignment][NFC] Transition to inferAlignFromPtrInfo
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2020-03-31 08:06:49 +00:00 |
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AMDGPUCallingConv.td
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[AMDGPU] Introduce more scratch registers in the ABI.
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2020-05-05 23:02:58 +05:30 |
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AMDGPUCodeGenPrepare.cpp
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[AMDGPU] Fix and simplify AMDGPUCodeGenPrepare::expandDivRem32
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2020-07-08 19:14:48 +01:00 |
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AMDGPUCombine.td
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AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
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2020-05-31 20:40:14 -04:00 |
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AMDGPUExportClustering.cpp
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[AMDGPU] Strengthen export cluster ordering
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2020-05-13 23:07:37 +09:00 |
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AMDGPUExportClustering.h
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[AMDGPU] Cluster shader exports
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2020-05-07 19:05:38 +09:00 |
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AMDGPUFeatures.td
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AMDGPU: Change internal tracking of wave size
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2020-06-01 17:55:08 -04:00 |
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AMDGPUFixFunctionBitcasts.cpp
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AMDGPU.h - reduce TargetMachine.h include. NFC.
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2020-05-24 15:27:41 +01:00 |
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AMDGPUFrameLowering.cpp
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…
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AMDGPUFrameLowering.h
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[Alignment][NFC] Deprecate Align::None()
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2020-01-24 12:53:58 +01:00 |
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AMDGPUGISel.td
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[llvm] NFC: Fix trivial typo in rst and td files
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2020-04-23 14:26:32 +09:00 |
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AMDGPUGenRegisterBankInfo.def
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[AMDGPU][GlobalISel] Revise handling of wide loads in RegBankSelect
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2020-05-11 18:10:16 -07:00 |
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AMDGPUGlobalISelUtils.cpp
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AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR
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2020-02-21 13:35:40 -05:00 |
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AMDGPUGlobalISelUtils.h
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AMDGPU/GlobalISel: Start selecting image intrinsics
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2020-03-30 17:33:04 -04:00 |
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AMDGPUHSAMetadataStreamer.cpp
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AMDGPU: Remove .value_type from kernel metadata
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2020-07-10 18:16:31 -04:00 |
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AMDGPUHSAMetadataStreamer.h
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AMDGPU: Remove .value_type from kernel metadata
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2020-07-10 18:16:31 -04:00 |
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AMDGPUISelDAGToDAG.cpp
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[SDAG] Add new AssertAlign ISD node.
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2020-06-23 00:51:11 -04:00 |
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AMDGPUISelLowering.cpp
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[AMDGPU] Fix typos in performCtlz_CttzCombine()
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2020-07-14 10:18:18 +01:00 |
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AMDGPUISelLowering.h
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AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
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2020-06-16 21:06:25 -04:00 |
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AMDGPUInline.cpp
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Revert "Revert "[llvm][NFC] Cleanup uses of std::function in Inlining-related APIs""
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2020-05-15 12:29:16 -07:00 |
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AMDGPUInstrInfo.cpp
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[AMDGPU] Remove AMDGPURegisterInfo
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2020-02-11 11:13:38 -08:00 |
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AMDGPUInstrInfo.h
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AMDGPU/GlobalISel: Change intrinsic ID for _L to _LZ opt
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2020-04-01 13:03:02 -04:00 |
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AMDGPUInstrInfo.td
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AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
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2020-06-16 21:06:25 -04:00 |
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AMDGPUInstructionSelector.cpp
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AMDGPU/GlobalISel: Select G_FREEZE
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2020-07-16 11:10:48 +02:00 |
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AMDGPUInstructionSelector.h
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[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
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2020-07-13 12:14:43 +02:00 |
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AMDGPUInstructions.td
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[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
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2020-07-08 19:14:49 +01:00 |
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AMDGPULegalizerInfo.cpp
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GlobalISel: Implement widenScalar for saturating add/sub
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2020-07-13 14:46:40 -04:00 |
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AMDGPULegalizerInfo.h
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AMDGPU/GlobalISel: Legalize 64-bit G_SDIV/G_SREM
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2020-06-24 11:39:45 -04:00 |
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AMDGPULibCalls.cpp
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[Alignment][NFC] Use proper getter to retrieve alignment from ConstantInt and ConstantSDNode
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2020-07-03 08:06:43 +00:00 |
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AMDGPULibFunc.cpp
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[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
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2020-05-29 17:54:17 -07:00 |
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AMDGPULibFunc.h
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AMDGPULibFunc - fix include order. NFC.
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2020-05-24 13:25:59 +01:00 |
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AMDGPULowerIntrinsics.cpp
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AMDGPU: Add flag to control mem intrinsic expansion
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2020-02-03 14:26:01 -08:00 |
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AMDGPULowerKernelArguments.cpp
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[Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment
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2020-07-01 14:31:56 +00:00 |
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AMDGPULowerKernelAttributes.cpp
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…
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AMDGPUMCInstLower.cpp
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[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
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2020-02-13 22:08:55 -08:00 |
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AMDGPUMachineCFGStructurizer.cpp
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…
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AMDGPUMachineFunction.cpp
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[Alignment][NFC] Migrate AMDGPU backend to Align
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2020-06-29 11:56:06 +00:00 |
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AMDGPUMachineFunction.h
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Remove GlobalValue::getAlignment().
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2020-06-23 19:13:42 -07:00 |
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AMDGPUMachineModuleInfo.cpp
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…
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AMDGPUMachineModuleInfo.h
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…
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AMDGPUMacroFusion.cpp
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[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
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2020-03-11 17:59:21 +00:00 |
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AMDGPUMacroFusion.h
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…
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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Avoid SmallString.h include in MD5.h, NFC
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2020-02-26 09:10:24 -08:00 |
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AMDGPUPTNote.h
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…
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AMDGPUPerfHintAnalysis.cpp
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AMDGPU.h - reduce TargetMachine.h include. NFC.
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2020-05-24 15:27:41 +01:00 |
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AMDGPUPerfHintAnalysis.h
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…
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AMDGPUPostLegalizerCombiner.cpp
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AMDGPU/GlobalISel: Fix asserts on non-s32 sitofp/uitofp sources
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2020-06-23 10:00:35 -04:00 |
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AMDGPUPreLegalizerCombiner.cpp
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[gicombiner] Allow generated combiners to store additional members
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2020-06-16 14:47:04 -07:00 |
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AMDGPUPrintfRuntimeBinding.cpp
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[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
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2020-05-29 17:54:17 -07:00 |
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AMDGPUPromoteAlloca.cpp
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[AMDGPU] Limit promote alloca to vector with VGPR budget
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2020-07-01 15:57:24 -07:00 |
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AMDGPUPropagateAttributes.cpp
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[AMDGPU] Propagate amdgpu-waves-per-eu to callees
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2020-03-26 14:43:44 -07:00 |
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AMDGPURegBankCombiner.cpp
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[gicombiner] Allow generated combiners to store additional members
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2020-06-16 14:47:04 -07:00 |
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AMDGPURegisterBankInfo.cpp
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AMDGPU/GlobalISel: Select G_FREEZE
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2020-07-16 11:10:48 +02:00 |
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AMDGPURegisterBankInfo.h
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AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads
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2020-06-15 11:33:16 -04:00 |
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AMDGPURegisterBanks.td
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[AMDGPU] Define AGPR subregs
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2020-04-28 15:30:43 -07:00 |
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AMDGPURewriteOutArguments.cpp
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[SVE] Remove usages of VectorType::getNumElements() from AMDGPU
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2020-05-13 15:57:55 -07:00 |
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AMDGPUSearchableTables.td
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[AMDGPU] Add gfx1030 target
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2020-06-15 16:18:05 -07:00 |
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AMDGPUSubtarget.cpp
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[AMDGPU] Simplify AMDGPUSubtarget::getWavesPerEU. NFC.
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2020-07-14 14:20:02 +01:00 |
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AMDGPUSubtarget.h
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AMDGPU: Don't pass MachineFunction if only the IR Function is used
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2020-06-18 11:06:46 -04:00 |
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AMDGPUTargetMachine.cpp
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[AMDGPU] Move LowerSwitch pass to CodeGenPrepare.
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2020-07-11 16:33:38 +05:30 |
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AMDGPUTargetMachine.h
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AMDGPU: Fix wrong null value for private address space
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2020-05-26 16:35:13 -04:00 |
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AMDGPUTargetObjectFile.cpp
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…
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AMDGPUTargetObjectFile.h
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AMDGPUTargetObjectFile.h - remove unnecessary includes. NFC.
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2020-05-24 13:57:02 +01:00 |
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AMDGPUTargetTransformInfo.cpp
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[AMDGPU][CostModel] Improve cost estimation for fused {fadd|fsub}(a,fmul(b,c))
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2020-07-16 03:06:38 +03:00 |
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AMDGPUTargetTransformInfo.h
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[NFC] Separate Peeling Properties into its own struct (re-land after minor fix)
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2020-07-10 18:39:30 +00:00 |
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AMDGPUUnifyDivergentExitNodes.cpp
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Revert "[NFC] SimplifyCFGOptions: drop multi-parameter ctor, use default member-init"
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2020-07-16 10:32:50 +02:00 |
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AMDGPUUnifyMetadata.cpp
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…
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AMDILCFGStructurizer.cpp
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…
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AMDKernelCodeT.h
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…
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BUFInstructions.td
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[AMDGPU][MC] Corrected MTBUF parsing and decoding
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2020-07-15 19:46:00 +03:00 |
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CMakeLists.txt
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AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
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2020-05-31 20:40:14 -04:00 |
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CaymanInstructions.td
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[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
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2020-07-08 19:14:49 +01:00 |
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DSInstructions.td
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[AMDGPU] Add gfx1030 target
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2020-06-15 16:18:05 -07:00 |
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EvergreenInstructions.td
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[TableGen] Drop deprecated leading # operation (NOP) and replace ## with #
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2020-04-25 16:26:45 -07:00 |
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FLATInstructions.td
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[AMDGPU] Add gfx1030 target
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2020-06-15 16:18:05 -07:00 |
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GCNDPPCombine.cpp
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[AMDGPU] Don't combine DPP if DPP register is used more than once per instruction
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2020-07-03 15:08:26 +03:00 |
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GCNHazardRecognizer.cpp
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[AMDGPU] Update VMEM scalar write hazard mitigation sequence
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2020-07-16 11:37:45 +09:00 |
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GCNHazardRecognizer.h
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[AMDGPU] Don't implement GCNHazardRecognizer::PreEmitNoops(SUnit *)
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2020-05-06 16:11:19 +01:00 |
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GCNILPSched.cpp
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…
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GCNIterativeScheduler.cpp
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[AMDGPU] Add file headers for few files where it is missing.
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2020-01-31 02:06:41 +05:30 |
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GCNIterativeScheduler.h
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[AMDGPU] Add file headers for few files where it is missing.
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2020-01-31 02:06:41 +05:30 |
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GCNMinRegStrategy.cpp
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SmallPtrSet::find -> SmallPtrSet::count
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2020-06-07 22:38:08 +02:00 |
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GCNNSAReassign.cpp
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AMDGPU/GFX10: Fix NSA reassign pass when operands are undef
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2020-02-01 22:41:40 +01:00 |
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GCNProcessors.td
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[AMDGPU] Add gfx1030 target
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2020-06-15 16:18:05 -07:00 |
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GCNRegBankReassign.cpp
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[AMDGPU] Use std::pair to return two values. NFC.
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2020-06-26 11:47:12 +01:00 |
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GCNRegPressure.cpp
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[AMDGPU] Fix assumption about LaneBitmask content
|
2020-02-19 09:07:11 -08:00 |
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GCNRegPressure.h
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Upgrade some instances of std::sort to llvm::sort. NFC.
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2020-03-28 19:23:29 +01:00 |
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GCNSchedStrategy.cpp
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[AMDGPU] Remove dubious logic in bidirectional list scheduler
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2020-02-28 21:35:34 +00:00 |
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GCNSchedStrategy.h
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[AMDGPU] Attempt to reschedule withou clustering
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2020-01-27 10:27:16 -08:00 |
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LLVMBuild.txt
|
…
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MIMGInstructions.td
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[AMDGPU] Add gfx1030 target
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2020-06-15 16:18:05 -07:00 |
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R600.td
|
…
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R600AsmPrinter.cpp
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[MC] Add MCStreamer::emitInt{8,16,32,64}
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2020-02-29 09:40:21 -08:00 |
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R600AsmPrinter.h
|
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
|
2020-02-13 22:08:55 -08:00 |
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R600ClauseMergePass.cpp
|
…
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R600ControlFlowFinalizer.cpp
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[AMDGPU] Make use of divideCeil. NFC.
|
2020-03-26 16:11:35 +00:00 |
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R600Defines.h
|
…
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R600EmitClauseMarkers.cpp
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…
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R600ExpandSpecialInstrs.cpp
|
[AMDGPU] Split R600 and GCN subregs
|
2020-02-10 08:29:56 -08:00 |
|
R600FrameLowering.cpp
|
CodeGen: Use Register in TargetFrameLowering
|
2020-04-07 17:07:44 -04:00 |
|
R600FrameLowering.h
|
CodeGen: Use Register in TargetFrameLowering
|
2020-04-07 17:07:44 -04:00 |
|
R600ISelLowering.cpp
|
[Alignment][NFC] Migrate AMDGPU backend to Align
|
2020-06-29 11:56:06 +00:00 |
|
R600ISelLowering.h
|
…
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R600InstrFormats.td
|
…
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|
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R600InstrInfo.cpp
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CodeGen: Use Register in TargetFrameLowering
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2020-04-07 17:07:44 -04:00 |
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R600InstrInfo.h
|
…
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|
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R600Instructions.td
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AMDGPU: Remove denormal subtarget features
|
2020-04-02 17:17:12 -04:00 |
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R600MachineFunctionInfo.cpp
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…
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R600MachineFunctionInfo.h
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…
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R600MachineScheduler.cpp
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…
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R600MachineScheduler.h
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…
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R600OpenCLImageTypeLoweringPass.cpp
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…
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R600OptimizeVectorRegisters.cpp
|
AMDGPU: Use Register
|
2020-06-30 12:13:08 -04:00 |
|
R600Packetizer.cpp
|
…
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R600Processors.td
|
…
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R600RegisterInfo.cpp
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[TBLGEN] Allow to override RC weight
|
2020-02-14 15:49:52 -08:00 |
|
R600RegisterInfo.h
|
[TBLGEN] Allow to override RC weight
|
2020-02-14 15:49:52 -08:00 |
|
R600RegisterInfo.td
|
[TBLGEN] Allow to override RC weight
|
2020-02-14 15:49:52 -08:00 |
|
R600Schedule.td
|
…
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|
R700Instructions.td
|
…
|
|
|
SIAddIMGInit.cpp
|
[AMDGPU] Split R600 and GCN subregs
|
2020-02-10 08:29:56 -08:00 |
|
SIAnnotateControlFlow.cpp
|
AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break
|
2020-02-03 07:02:05 -08:00 |
|
SIDefines.h
|
[AMDGPU][MC] Corrected MTBUF parsing and decoding
|
2020-07-15 19:46:00 +03:00 |
|
SIFixSGPRCopies.cpp
|
[AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate
|
2020-05-28 19:25:51 +03:00 |
|
SIFixVGPRCopies.cpp
|
…
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|
|
SIFixupVectorISel.cpp
|
AMDGPU/GlobalISel: Skip DAG hack passes on selected functions
|
2020-02-17 08:33:17 -08:00 |
|
SIFoldOperands.cpp
|
AMDGPU: Clear subreg when folding immediate copies
|
2020-07-01 13:59:13 -04:00 |
|
SIFormMemoryClauses.cpp
|
…
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SIFrameLowering.cpp
|
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
|
2020-07-01 07:28:11 +00:00 |
|
SIFrameLowering.h
|
For PAL, make sure Scratch Buffer Descriptor do not clobber GIT pointer
|
2020-05-06 10:31:15 -04:00 |
|
SIISelLowering.cpp
|
[NFC] Change isFPPredicate comparison to ignore lower bound
|
2020-07-10 11:57:20 +01:00 |
|
SIISelLowering.h
|
[AMDGPU] Tweak getTypeLegalizationCost()
|
2020-07-06 14:07:48 -07:00 |
|
SIInsertHardClauses.cpp
|
[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
|
2020-06-01 22:52:34 +05:30 |
|
SIInsertSkips.cpp
|
[AMDGPU] Insert PS early exit at end of control flow
|
2020-07-03 14:04:34 +09:00 |
|
SIInsertWaitcnts.cpp
|
[AMDGPU] Skip CFIInstructions in SIInsertWaitcnts
|
2020-06-17 12:41:03 -04:00 |
|
SIInstrFormats.td
|
AMDGPU: Start adding MODE register uses to instructions
|
2020-05-27 14:47:00 -04:00 |
|
SIInstrInfo.cpp
|
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
|
2020-07-01 18:58:59 -04:00 |
|
SIInstrInfo.h
|
[AMDGPU] Select s_cselect
|
2020-06-25 10:38:23 +02:00 |
|
SIInstrInfo.td
|
[AMDGPU][MC] Corrected MTBUF parsing and decoding
|
2020-07-15 19:46:00 +03:00 |
|
SIInstructions.td
|
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
|
2020-07-08 19:14:49 +01:00 |
|
SILoadStoreOptimizer.cpp
|
SILoadStoreOptimizer: add support for GFX10 image instructions
|
2020-07-08 19:15:46 +01:00 |
|
SILowerControlFlow.cpp
|
[AMDGPU] Insert PS early exit at end of control flow
|
2020-07-03 14:04:34 +09:00 |
|
SILowerI1Copies.cpp
|
AMDGPU/GlobalISel: Skip DAG hack passes on selected functions
|
2020-02-17 08:33:17 -08:00 |
|
SILowerSGPRSpills.cpp
|
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
|
2020-07-01 07:28:11 +00:00 |
|
SIMachineFunctionInfo.cpp
|
[AMDGPU] Spill more than wavesize CSR SGPRs
|
2020-07-01 07:40:47 +00:00 |
|
SIMachineFunctionInfo.h
|
AMDGPU/GlobalISel: Add types to special inputs
|
2020-07-06 17:00:55 -04:00 |
|
SIMachineScheduler.cpp
|
[AMDGPU] Use generated RegisterPressureSets enum
|
2020-02-18 10:34:03 -08:00 |
|
SIMachineScheduler.h
|
[AMDGPU] Use generated RegisterPressureSets enum
|
2020-02-18 10:34:03 -08:00 |
|
SIMemoryLegalizer.cpp
|
[AMDGPU] Skip generating cache invalidating instructions on AMDPAL
|
2020-04-24 13:53:44 +02:00 |
|
SIModeRegister.cpp
|
[AMDGPU] Avoid redundant mode register writes
|
2020-06-24 14:11:29 +01:00 |
|
SIOptimizeExecMasking.cpp
|
…
|
|
|
SIOptimizeExecMaskingPreRA.cpp
|
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
|
2020-07-14 12:53:43 +09:00 |
|
SIPeepholeSDWA.cpp
|
AMDGPU: Fix dropping MI flags when rewriting instructions
|
2020-05-27 13:27:06 -04:00 |
|
SIPostRABundler.cpp
|
AMDGPU: Do not bundle inline asm
|
2020-06-14 13:24:50 -04:00 |
|
SIPreAllocateWWMRegs.cpp
|
…
|
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SIPreEmitPeephole.cpp
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[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
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2020-07-15 11:02:35 +09:00 |
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SIProgramInfo.h
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…
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|
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SIRegisterInfo.cpp
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AMDGPU: Use Register
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2020-06-30 12:13:08 -04:00 |
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SIRegisterInfo.h
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[NFC] Move getAll{S,V}GPR{32,128} methods to SIFrameLowering
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2020-06-17 12:08:09 -04:00 |
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SIRegisterInfo.td
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AMDGPU: Define mode register
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2020-05-23 13:24:42 -04:00 |
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SIRemoveShortExecBranches.cpp
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[AMDGPU] Don't remove short branches over kills
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2020-02-03 09:26:52 +00:00 |
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SISchedule.td
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[AMDGPU] More accurate gfx10 latencies
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2020-06-04 10:29:32 +01:00 |
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SIShrinkInstructions.cpp
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[AMDGPU] Avoid using s_cmpk when src0 is not register
|
2020-07-14 09:05:53 +01:00 |
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SIWholeQuadMode.cpp
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[AMDGPU] Update more live intervals in SIWholeQuadMode
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2020-06-22 13:50:15 +01:00 |
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SMInstructions.td
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AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
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2020-06-18 14:12:19 -04:00 |
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SOPInstructions.td
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[AMDGPU] Select s_cselect
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2020-06-25 10:38:23 +02:00 |
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VIInstrFormats.td
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…
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|
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VOP1Instructions.td
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AMDGPU: Add llvm.amdgcn.sqrt intrinsic
|
2020-06-26 15:07:07 -04:00 |
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VOP2Instructions.td
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AMDGPU: Don't use 16-bit FP inline constants in integer operands
|
2020-06-17 19:14:10 -04:00 |
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VOP3Instructions.td
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AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
|
2020-06-16 21:06:25 -04:00 |
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VOP3PInstructions.td
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AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
|
2020-07-01 18:58:59 -04:00 |
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VOPCInstructions.td
|
AMDGPU: Start adding MODE register uses to instructions
|
2020-05-27 14:47:00 -04:00 |
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VOPInstructions.td
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AMDGPU: Set mayRaiseFPException
|
2020-06-04 17:35:27 -04:00 |
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