forked from OSchip/llvm-project
291 lines
10 KiB
LLVM
291 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @test(i256* %a, i256* %b, i256* %out) #0 {
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; X32-LABEL: test:
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; X32: # BB#0: # %entry
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; X32-NEXT: pushl %ebp
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; X32-NEXT: .Lcfi0:
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: .Lcfi1:
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; X32-NEXT: .cfi_offset %ebp, -8
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: .Lcfi2:
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; X32-NEXT: .cfi_def_cfa_register %ebp
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; X32-NEXT: pushl %ebx
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %esi
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; X32-NEXT: andl $-8, %esp
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; X32-NEXT: subl $168, %esp
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; X32-NEXT: .Lcfi3:
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; X32-NEXT: .cfi_offset %esi, -20
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; X32-NEXT: .Lcfi4:
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; X32-NEXT: .cfi_offset %edi, -16
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; X32-NEXT: .Lcfi5:
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; X32-NEXT: .cfi_offset %ebx, -12
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; X32-NEXT: movl 8(%ebp), %eax
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; X32-NEXT: movl 16(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 20(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 24(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 28(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 8(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 12(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl (%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 4(%eax), %ebx
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; X32-NEXT: movl 12(%ebp), %eax
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; X32-NEXT: movl 16(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 20(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 24(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 28(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl (%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 4(%eax), %ecx
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl 8(%eax), %esi
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; X32-NEXT: movl 12(%eax), %edi
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; X32-NEXT: leal {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl %edi
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; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: pushl %esi
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; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl %ebx
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl %eax
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; X32-NEXT: calll __multi3
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; X32-NEXT: addl $32, %esp
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; X32-NEXT: leal {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %esi
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi # 4-byte Reload
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; X32-NEXT: pushl %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi # 4-byte Reload
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %eax
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; X32-NEXT: calll __multi3
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; X32-NEXT: addl $32, %esp
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; X32-NEXT: leal {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl %ebx
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl %eax
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; X32-NEXT: calll __multi3
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; X32-NEXT: addl $32, %esp
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; X32-NEXT: leal {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pushl %esi
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %ebx
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl %eax
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; X32-NEXT: calll __multi3
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; X32-NEXT: addl $32, %esp
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; X32-NEXT: leal {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl %esi
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %eax
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; X32-NEXT: calll __multi3
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; X32-NEXT: addl $32, %esp
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: addl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: adcl $0, %ecx
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; X32-NEXT: adcl $0, %eax
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; X32-NEXT: addl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: adcl $0, %edi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; X32-NEXT: adcl $0, %ebx
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; X32-NEXT: xorl %edx, %edx
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; X32-NEXT: addl %ecx, %edi
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; X32-NEXT: adcl %eax, %ebx
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; X32-NEXT: adcl $0, %edx
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; X32-NEXT: sbbl %eax, %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: addl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %ebx
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: leal {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl {{[0-9]+}}(%esp) # 4-byte Folded Reload
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; X32-NEXT: pushl %eax
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; X32-NEXT: calll __multi3
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; X32-NEXT: addl $32, %esp
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: addl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: addl %edi, %esi
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; X32-NEXT: adcl %ebx, %ecx
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %edx # 4-byte Folded Reload
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; X32-NEXT: adcl {{[0-9]+}}(%esp), %eax # 4-byte Folded Reload
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; X32-NEXT: movl 16(%ebp), %edi
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; X32-NEXT: movl %ebx, 4(%edi)
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; X32-NEXT: movl 16(%ebp), %ebx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi # 4-byte Reload
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; X32-NEXT: movl %edi, (%ebx)
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi # 4-byte Reload
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; X32-NEXT: movl %edi, 8(%ebx)
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi # 4-byte Reload
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; X32-NEXT: movl %edi, 12(%ebx)
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; X32-NEXT: movl %esi, 16(%ebx)
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; X32-NEXT: movl %ecx, 20(%ebx)
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; X32-NEXT: movl %edx, 24(%ebx)
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; X32-NEXT: movl %eax, 28(%ebx)
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; X32-NEXT: leal -12(%ebp), %esp
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; X32-NEXT: popl %esi
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; X32-NEXT: popl %edi
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; X32-NEXT: popl %ebx
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; X32-NEXT: popl %ebp
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; X32-NEXT: retl
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;
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; X64-LABEL: test:
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; X64: # BB#0: # %entry
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; X64-NEXT: pushq %r15
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; X64-NEXT: .Lcfi0:
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; X64-NEXT: .cfi_def_cfa_offset 16
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; X64-NEXT: pushq %r14
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; X64-NEXT: .Lcfi1:
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; X64-NEXT: .cfi_def_cfa_offset 24
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; X64-NEXT: pushq %r12
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; X64-NEXT: .Lcfi2:
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; X64-NEXT: .cfi_def_cfa_offset 32
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; X64-NEXT: pushq %rbx
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; X64-NEXT: .Lcfi3:
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; X64-NEXT: .cfi_def_cfa_offset 40
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; X64-NEXT: .Lcfi4:
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; X64-NEXT: .cfi_offset %rbx, -40
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; X64-NEXT: .Lcfi5:
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; X64-NEXT: .cfi_offset %r12, -32
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; X64-NEXT: .Lcfi6:
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; X64-NEXT: .cfi_offset %r14, -24
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; X64-NEXT: .Lcfi7:
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; X64-NEXT: .cfi_offset %r15, -16
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; X64-NEXT: movq %rdx, %r10
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; X64-NEXT: movq (%rdi), %r14
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; X64-NEXT: movq 8(%rdi), %r8
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; X64-NEXT: movq 16(%rdi), %rcx
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; X64-NEXT: movq 16(%rsi), %rbx
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; X64-NEXT: movq (%rsi), %r12
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; X64-NEXT: movq 8(%rsi), %r15
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; X64-NEXT: movq 24(%rdi), %rdi
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; X64-NEXT: imulq %r12, %rdi
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; X64-NEXT: movq %r12, %rax
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; X64-NEXT: mulq %rcx
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; X64-NEXT: movq %rax, %r9
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; X64-NEXT: addq %rdi, %rdx
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; X64-NEXT: imulq %r15, %rcx
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; X64-NEXT: addq %rdx, %rcx
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; X64-NEXT: movq %rbx, %rdi
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; X64-NEXT: imulq %r8, %rdi
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; X64-NEXT: movq %rbx, %rax
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; X64-NEXT: mulq %r14
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; X64-NEXT: movq %rax, %r11
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; X64-NEXT: addq %rdi, %rdx
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; X64-NEXT: movq 24(%rsi), %rbx
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; X64-NEXT: imulq %r14, %rbx
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; X64-NEXT: addq %rdx, %rbx
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; X64-NEXT: addq %r9, %r11
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; X64-NEXT: adcq %rcx, %rbx
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; X64-NEXT: movq %r14, %rax
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; X64-NEXT: mulq %r12
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; X64-NEXT: movq %rdx, %rsi
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; X64-NEXT: movq %rax, %r9
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; X64-NEXT: movq %r8, %rax
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; X64-NEXT: mulq %r12
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; X64-NEXT: movq %rdx, %rcx
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; X64-NEXT: movq %rax, %rdi
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; X64-NEXT: addq %rsi, %rdi
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; X64-NEXT: adcq $0, %rcx
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; X64-NEXT: movq %r14, %rax
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; X64-NEXT: mulq %r15
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; X64-NEXT: movq %rdx, %rsi
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; X64-NEXT: movq %rax, %r14
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; X64-NEXT: addq %rdi, %r14
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; X64-NEXT: adcq $0, %rsi
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; X64-NEXT: addq %rcx, %rsi
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; X64-NEXT: sbbq %rcx, %rcx
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; X64-NEXT: andl $1, %ecx
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; X64-NEXT: movq %r8, %rax
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; X64-NEXT: mulq %r15
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; X64-NEXT: addq %rsi, %rax
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; X64-NEXT: adcq %rcx, %rdx
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; X64-NEXT: addq %r11, %rax
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; X64-NEXT: adcq %rbx, %rdx
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; X64-NEXT: movq %r9, (%r10)
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; X64-NEXT: movq %r14, 8(%r10)
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; X64-NEXT: movq %rax, 16(%r10)
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; X64-NEXT: movq %rdx, 24(%r10)
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; X64-NEXT: popq %rbx
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; X64-NEXT: popq %r12
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; X64-NEXT: popq %r14
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; X64-NEXT: popq %r15
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; X64-NEXT: retq
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entry:
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%av = load i256, i256* %a
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%bv = load i256, i256* %b
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%r = mul i256 %av, %bv
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store i256 %r, i256* %out
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ret void
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}
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attributes #0 = { norecurse nounwind uwtable "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" }
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