forked from OSchip/llvm-project
43 lines
2.4 KiB
LLVM
43 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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; This test checks optimal passing values between "cmp" and "kor" intrinsics
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; PR28839
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone uwtable
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define zeroext i16 @cmp_kor_seq_16(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x float> %d, <16 x float> %x) local_unnamed_addr #0 {
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; CHECK-LABEL: cmp_kor_seq_16:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vcmpgeps %zmm4, %zmm0, %k0
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; CHECK-NEXT: vcmpgeps %zmm4, %zmm1, %k1
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; CHECK-NEXT: vcmpgeps %zmm4, %zmm2, %k2
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; CHECK-NEXT: vcmpgeps %zmm4, %zmm3, %k3
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; CHECK-NEXT: korw %k1, %k0, %k0
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; CHECK-NEXT: korw %k3, %k2, %k1
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; CHECK-NEXT: korw %k1, %k0, %k0
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; CHECK-NEXT: kmovw %k0, %eax
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; CHECK-NEXT: retq
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entry:
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%0 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %x, i32 13, i16 -1, i32 4)
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%1 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %b, <16 x float> %x, i32 13, i16 -1, i32 4)
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%2 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %c, <16 x float> %x, i32 13, i16 -1, i32 4)
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%3 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %d, <16 x float> %x, i32 13, i16 -1, i32 4)
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%4 = tail call i16 @llvm.x86.avx512.kor.w(i16 %0, i16 %1) #2
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%5 = tail call i16 @llvm.x86.avx512.kor.w(i16 %2, i16 %3) #2
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%6 = tail call i16 @llvm.x86.avx512.kor.w(i16 %4, i16 %5) #2
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ret i16 %6
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}
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; Function Attrs: nounwind readnone
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declare i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, i16, i32) #1
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; Function Attrs: nounwind readnone
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declare i16 @llvm.x86.avx512.kor.w(i16, i16) #1
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attributes #0 = { nounwind readnone uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="knl" "target-features"="+adx,+aes,+avx,+avx2,+avx512cd,+avx512er,+avx512f,+avx512pf,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prefetchwt1,+rdrnd,+rdseed,+rtm,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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