forked from OSchip/llvm-project
593 lines
22 KiB
C++
593 lines
22 KiB
C++
//===- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the VirtRegMap class.
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//
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// It also contains implementations of the Spiller interface, which, given a
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// virtual register map and a machine function, eliminates all virtual
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// references by replacing them with physical register references - adding spill
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// code as necessary.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "LiveDebugVariables.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveStacks.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <iterator>
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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STATISTIC(NumSpillSlots, "Number of spill slots allocated");
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STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
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//===----------------------------------------------------------------------===//
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// VirtRegMap implementation
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//===----------------------------------------------------------------------===//
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char VirtRegMap::ID = 0;
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INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
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bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
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MRI = &mf.getRegInfo();
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TII = mf.getSubtarget().getInstrInfo();
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TRI = mf.getSubtarget().getRegisterInfo();
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MF = &mf;
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Virt2PhysMap.clear();
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Virt2StackSlotMap.clear();
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Virt2SplitMap.clear();
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grow();
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return false;
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}
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void VirtRegMap::grow() {
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unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
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Virt2PhysMap.resize(NumRegs);
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Virt2StackSlotMap.resize(NumRegs);
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Virt2SplitMap.resize(NumRegs);
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}
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void VirtRegMap::assignVirt2Phys(Register virtReg, MCPhysReg physReg) {
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assert(virtReg.isVirtual() && Register::isPhysicalRegister(physReg));
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assert(Virt2PhysMap[virtReg.id()] == NO_PHYS_REG &&
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"attempt to assign physical register to already mapped "
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"virtual register");
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assert(!getRegInfo().isReserved(physReg) &&
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"Attempt to map virtReg to a reserved physReg");
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Virt2PhysMap[virtReg.id()] = physReg;
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}
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unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
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unsigned Size = TRI->getSpillSize(*RC);
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Align Alignment = TRI->getSpillAlign(*RC);
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int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Alignment);
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++NumSpillSlots;
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return SS;
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}
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bool VirtRegMap::hasPreferredPhys(Register VirtReg) {
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Register Hint = MRI->getSimpleHint(VirtReg);
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if (!Hint.isValid())
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return false;
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if (Hint.isVirtual())
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Hint = getPhys(Hint);
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return Register(getPhys(VirtReg)) == Hint;
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}
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bool VirtRegMap::hasKnownPreference(Register VirtReg) {
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std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
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if (Register::isPhysicalRegister(Hint.second))
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return true;
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if (Register::isVirtualRegister(Hint.second))
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return hasPhys(Hint.second);
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return false;
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}
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int VirtRegMap::assignVirt2StackSlot(Register virtReg) {
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assert(virtReg.isVirtual());
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assert(Virt2StackSlotMap[virtReg.id()] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
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return Virt2StackSlotMap[virtReg.id()] = createSpillSlot(RC);
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}
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void VirtRegMap::assignVirt2StackSlot(Register virtReg, int SS) {
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assert(virtReg.isVirtual());
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assert(Virt2StackSlotMap[virtReg.id()] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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assert((SS >= 0 ||
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(SS >= MF->getFrameInfo().getObjectIndexBegin())) &&
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"illegal fixed frame index");
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Virt2StackSlotMap[virtReg.id()] = SS;
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}
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void VirtRegMap::print(raw_ostream &OS, const Module*) const {
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OS << "********** REGISTER MAP **********\n";
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = Register::index2VirtReg(i);
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if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
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OS << '[' << printReg(Reg, TRI) << " -> "
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<< printReg(Virt2PhysMap[Reg], TRI) << "] "
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<< TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
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}
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}
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = Register::index2VirtReg(i);
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if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
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OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
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<< "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
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}
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}
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OS << '\n';
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD void VirtRegMap::dump() const {
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print(dbgs());
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}
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#endif
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//===----------------------------------------------------------------------===//
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// VirtRegRewriter
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//===----------------------------------------------------------------------===//
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//
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// The VirtRegRewriter is the last of the register allocator passes.
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// It rewrites virtual registers to physical registers as specified in the
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// VirtRegMap analysis. It also updates live-in information on basic blocks
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// according to LiveIntervals.
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//
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namespace {
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class VirtRegRewriter : public MachineFunctionPass {
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MachineFunction *MF;
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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SlotIndexes *Indexes;
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LiveIntervals *LIS;
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VirtRegMap *VRM;
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void rewrite();
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void addMBBLiveIns();
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bool readsUndefSubreg(const MachineOperand &MO) const;
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void addLiveInsForSubRanges(const LiveInterval &LI, Register PhysReg) const;
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void handleIdentityCopy(MachineInstr &MI) const;
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void expandCopyBundle(MachineInstr &MI) const;
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bool subRegLiveThrough(const MachineInstr &MI, Register SuperPhysReg) const;
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public:
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static char ID;
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VirtRegRewriter() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction&) override;
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MachineFunctionProperties getSetProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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};
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} // end anonymous namespace
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char VirtRegRewriter::ID = 0;
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char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
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INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
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"Virtual Register Rewriter", false, false)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
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INITIALIZE_PASS_DEPENDENCY(LiveStacks)
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INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
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"Virtual Register Rewriter", false, false)
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void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<LiveIntervals>();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveDebugVariables>();
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AU.addRequired<LiveStacks>();
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AU.addPreserved<LiveStacks>();
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AU.addRequired<VirtRegMap>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
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MF = &fn;
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TRI = MF->getSubtarget().getRegisterInfo();
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TII = MF->getSubtarget().getInstrInfo();
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MRI = &MF->getRegInfo();
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Indexes = &getAnalysis<SlotIndexes>();
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LIS = &getAnalysis<LiveIntervals>();
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VRM = &getAnalysis<VirtRegMap>();
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LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
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<< "********** Function: " << MF->getName() << '\n');
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LLVM_DEBUG(VRM->dump());
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// Add kill flags while we still have virtual registers.
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LIS->addKillFlags(VRM);
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// Live-in lists on basic blocks are required for physregs.
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addMBBLiveIns();
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// Rewrite virtual registers.
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rewrite();
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// Write out new DBG_VALUE instructions.
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getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
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// All machine operands and other references to virtual registers have been
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// replaced. Remove the virtual registers and release all the transient data.
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VRM->clearAllVirt();
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MRI->clearVirtRegs();
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return true;
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}
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void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
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Register PhysReg) const {
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assert(!LI.empty());
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assert(LI.hasSubRanges());
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using SubRangeIteratorPair =
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std::pair<const LiveInterval::SubRange *, LiveInterval::const_iterator>;
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SmallVector<SubRangeIteratorPair, 4> SubRanges;
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SlotIndex First;
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SlotIndex Last;
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for (const LiveInterval::SubRange &SR : LI.subranges()) {
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SubRanges.push_back(std::make_pair(&SR, SR.begin()));
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if (!First.isValid() || SR.segments.front().start < First)
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First = SR.segments.front().start;
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if (!Last.isValid() || SR.segments.back().end > Last)
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Last = SR.segments.back().end;
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}
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// Check all mbb start positions between First and Last while
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// simulatenously advancing an iterator for each subrange.
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for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
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MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
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SlotIndex MBBBegin = MBBI->first;
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// Advance all subrange iterators so that their end position is just
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// behind MBBBegin (or the iterator is at the end).
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LaneBitmask LaneMask;
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for (auto &RangeIterPair : SubRanges) {
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const LiveInterval::SubRange *SR = RangeIterPair.first;
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LiveInterval::const_iterator &SRI = RangeIterPair.second;
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while (SRI != SR->end() && SRI->end <= MBBBegin)
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++SRI;
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if (SRI == SR->end())
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continue;
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if (SRI->start <= MBBBegin)
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LaneMask |= SR->LaneMask;
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}
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if (LaneMask.none())
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continue;
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MachineBasicBlock *MBB = MBBI->second;
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MBB->addLiveIn(PhysReg, LaneMask);
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}
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}
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// Compute MBB live-in lists from virtual register live ranges and their
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// assignments.
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void VirtRegRewriter::addMBBLiveIns() {
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for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
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Register VirtReg = Register::index2VirtReg(Idx);
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if (MRI->reg_nodbg_empty(VirtReg))
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continue;
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LiveInterval &LI = LIS->getInterval(VirtReg);
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if (LI.empty() || LIS->intervalIsInOneMBB(LI))
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continue;
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// This is a virtual register that is live across basic blocks. Its
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// assigned PhysReg must be marked as live-in to those blocks.
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Register PhysReg = VRM->getPhys(VirtReg);
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assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
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if (LI.hasSubRanges()) {
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addLiveInsForSubRanges(LI, PhysReg);
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} else {
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// Go over MBB begin positions and see if we have segments covering them.
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// The following works because segments and the MBBIndex list are both
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// sorted by slot indexes.
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SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin();
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for (const auto &Seg : LI) {
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I = Indexes->advanceMBBIndex(I, Seg.start);
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for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {
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MachineBasicBlock *MBB = I->second;
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MBB->addLiveIn(PhysReg);
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}
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}
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}
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}
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// Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
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// each MBB's LiveIns set before calling addLiveIn on them.
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for (MachineBasicBlock &MBB : *MF)
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MBB.sortUniqueLiveIns();
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}
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/// Returns true if the given machine operand \p MO only reads undefined lanes.
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/// The function only works for use operands with a subregister set.
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bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
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// Shortcut if the operand is already marked undef.
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if (MO.isUndef())
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return true;
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Register Reg = MO.getReg();
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const LiveInterval &LI = LIS->getInterval(Reg);
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const MachineInstr &MI = *MO.getParent();
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SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
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// This code is only meant to handle reading undefined subregisters which
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// we couldn't properly detect before.
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assert(LI.liveAt(BaseIndex) &&
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"Reads of completely dead register should be marked undef already");
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unsigned SubRegIdx = MO.getSubReg();
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assert(SubRegIdx != 0 && LI.hasSubRanges());
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LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
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// See if any of the relevant subregister liveranges is defined at this point.
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for (const LiveInterval::SubRange &SR : LI.subranges()) {
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if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
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return false;
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}
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return true;
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}
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void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const {
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if (!MI.isIdentityCopy())
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return;
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LLVM_DEBUG(dbgs() << "Identity copy: " << MI);
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++NumIdCopies;
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// Copies like:
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// %r0 = COPY undef %r0
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// %al = COPY %al, implicit-def %eax
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// give us additional liveness information: The target (super-)register
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// must not be valid before this point. Replace the COPY with a KILL
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// instruction to maintain this information.
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if (MI.getOperand(1).isUndef() || MI.getNumOperands() > 2) {
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MI.setDesc(TII->get(TargetOpcode::KILL));
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LLVM_DEBUG(dbgs() << " replace by: " << MI);
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return;
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}
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if (Indexes)
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Indexes->removeSingleMachineInstrFromMaps(MI);
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MI.eraseFromBundle();
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LLVM_DEBUG(dbgs() << " deleted.\n");
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}
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/// The liverange splitting logic sometimes produces bundles of copies when
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/// subregisters are involved. Expand these into a sequence of copy instructions
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/// after processing the last in the bundle. Does not update LiveIntervals
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/// which we shouldn't need for this instruction anymore.
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void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {
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if (!MI.isCopy() && !MI.isKill())
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return;
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if (MI.isBundledWithPred() && !MI.isBundledWithSucc()) {
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SmallVector<MachineInstr *, 2> MIs({&MI});
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// Only do this when the complete bundle is made out of COPYs and KILLs.
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MachineBasicBlock &MBB = *MI.getParent();
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for (MachineBasicBlock::reverse_instr_iterator I =
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std::next(MI.getReverseIterator()), E = MBB.instr_rend();
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I != E && I->isBundledWithSucc(); ++I) {
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if (!I->isCopy() && !I->isKill())
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return;
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MIs.push_back(&*I);
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}
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MachineInstr *FirstMI = MIs.back();
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auto anyRegsAlias = [](const MachineInstr *Dst,
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ArrayRef<MachineInstr *> Srcs,
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const TargetRegisterInfo *TRI) {
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for (const MachineInstr *Src : Srcs)
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if (Src != Dst)
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if (TRI->regsOverlap(Dst->getOperand(0).getReg(),
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Src->getOperand(1).getReg()))
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return true;
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return false;
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};
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// If any of the destination registers in the bundle of copies alias any of
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// the source registers, try to schedule the instructions to avoid any
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// clobbering.
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for (int E = MIs.size(), PrevE = E; E > 1; PrevE = E) {
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for (int I = E; I--; )
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if (!anyRegsAlias(MIs[I], makeArrayRef(MIs).take_front(E), TRI)) {
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if (I + 1 != E)
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std::swap(MIs[I], MIs[E - 1]);
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--E;
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}
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if (PrevE == E) {
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MF->getFunction().getContext().emitError(
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"register rewriting failed: cycle in copy bundle");
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break;
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}
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}
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MachineInstr *BundleStart = FirstMI;
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for (MachineInstr *BundledMI : llvm::reverse(MIs)) {
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// If instruction is in the middle of the bundle, move it before the
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// bundle starts, otherwise, just unbundle it. When we get to the last
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// instruction, the bundle will have been completely undone.
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if (BundledMI != BundleStart) {
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BundledMI->removeFromBundle();
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MBB.insert(BundleStart, BundledMI);
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} else if (BundledMI->isBundledWithSucc()) {
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BundledMI->unbundleFromSucc();
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BundleStart = &*std::next(BundledMI->getIterator());
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}
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if (Indexes && BundledMI != FirstMI)
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Indexes->insertMachineInstrInMaps(*BundledMI);
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}
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}
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}
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/// Check whether (part of) \p SuperPhysReg is live through \p MI.
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/// \pre \p MI defines a subregister of a virtual register that
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/// has been assigned to \p SuperPhysReg.
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|
bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
|
|
Register SuperPhysReg) const {
|
|
SlotIndex MIIndex = LIS->getInstructionIndex(MI);
|
|
SlotIndex BeforeMIUses = MIIndex.getBaseIndex();
|
|
SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex();
|
|
for (MCRegUnitIterator Unit(SuperPhysReg, TRI); Unit.isValid(); ++Unit) {
|
|
const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
|
|
// If the regunit is live both before and after MI,
|
|
// we assume it is live through.
|
|
// Generally speaking, this is not true, because something like
|
|
// "RU = op RU" would match that description.
|
|
// However, we know that we are trying to assess whether
|
|
// a def of a virtual reg, vreg, is live at the same time of RU.
|
|
// If we are in the "RU = op RU" situation, that means that vreg
|
|
// is defined at the same time as RU (i.e., "vreg, RU = op RU").
|
|
// Thus, vreg and RU interferes and vreg cannot be assigned to
|
|
// SuperPhysReg. Therefore, this situation cannot happen.
|
|
if (UnitRange.liveAt(AfterMIDefs) && UnitRange.liveAt(BeforeMIUses))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void VirtRegRewriter::rewrite() {
|
|
bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
|
|
SmallVector<Register, 8> SuperDeads;
|
|
SmallVector<Register, 8> SuperDefs;
|
|
SmallVector<Register, 8> SuperKills;
|
|
|
|
for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
|
|
MBBI != MBBE; ++MBBI) {
|
|
LLVM_DEBUG(MBBI->print(dbgs(), Indexes));
|
|
for (MachineBasicBlock::instr_iterator
|
|
MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
|
|
MachineInstr *MI = &*MII;
|
|
++MII;
|
|
|
|
for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
|
|
MOE = MI->operands_end(); MOI != MOE; ++MOI) {
|
|
MachineOperand &MO = *MOI;
|
|
|
|
// Make sure MRI knows about registers clobbered by regmasks.
|
|
if (MO.isRegMask())
|
|
MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
|
|
|
|
if (!MO.isReg() || !MO.getReg().isVirtual())
|
|
continue;
|
|
Register VirtReg = MO.getReg();
|
|
Register PhysReg = VRM->getPhys(VirtReg);
|
|
assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
|
|
"Instruction uses unmapped VirtReg");
|
|
assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
|
|
|
|
// Preserve semantics of sub-register operands.
|
|
unsigned SubReg = MO.getSubReg();
|
|
if (SubReg != 0) {
|
|
if (NoSubRegLiveness || !MRI->shouldTrackSubRegLiveness(VirtReg)) {
|
|
// A virtual register kill refers to the whole register, so we may
|
|
// have to add implicit killed operands for the super-register. A
|
|
// partial redef always kills and redefines the super-register.
|
|
if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
|
|
(MO.isDef() && subRegLiveThrough(*MI, PhysReg)))
|
|
SuperKills.push_back(PhysReg);
|
|
|
|
if (MO.isDef()) {
|
|
// Also add implicit defs for the super-register.
|
|
if (MO.isDead())
|
|
SuperDeads.push_back(PhysReg);
|
|
else
|
|
SuperDefs.push_back(PhysReg);
|
|
}
|
|
} else {
|
|
if (MO.isUse()) {
|
|
if (readsUndefSubreg(MO))
|
|
// We need to add an <undef> flag if the subregister is
|
|
// completely undefined (and we are not adding super-register
|
|
// defs).
|
|
MO.setIsUndef(true);
|
|
} else if (!MO.isDead()) {
|
|
assert(MO.isDef());
|
|
}
|
|
}
|
|
|
|
// The def undef and def internal flags only make sense for
|
|
// sub-register defs, and we are substituting a full physreg. An
|
|
// implicit killed operand from the SuperKills list will represent the
|
|
// partial read of the super-register.
|
|
if (MO.isDef()) {
|
|
MO.setIsUndef(false);
|
|
MO.setIsInternalRead(false);
|
|
}
|
|
|
|
// PhysReg operands cannot have subregister indexes.
|
|
PhysReg = TRI->getSubReg(PhysReg, SubReg);
|
|
assert(PhysReg.isValid() && "Invalid SubReg for physical register");
|
|
MO.setSubReg(0);
|
|
}
|
|
// Rewrite. Note we could have used MachineOperand::substPhysReg(), but
|
|
// we need the inlining here.
|
|
MO.setReg(PhysReg);
|
|
MO.setIsRenamable(true);
|
|
}
|
|
|
|
// Add any missing super-register kills after rewriting the whole
|
|
// instruction.
|
|
while (!SuperKills.empty())
|
|
MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
|
|
|
|
while (!SuperDeads.empty())
|
|
MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
|
|
|
|
while (!SuperDefs.empty())
|
|
MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
|
|
|
|
LLVM_DEBUG(dbgs() << "> " << *MI);
|
|
|
|
expandCopyBundle(*MI);
|
|
|
|
// We can remove identity copies right now.
|
|
handleIdentityCopy(*MI);
|
|
}
|
|
}
|
|
}
|