forked from OSchip/llvm-project
120 lines
4.2 KiB
C++
120 lines
4.2 KiB
C++
//===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements an allocation order for virtual registers.
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//
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// The preferred allocation order for a virtual register depends on allocation
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// hints and target hooks. The AllocationOrder class encapsulates all of that.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
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#define LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCRegister.h"
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namespace llvm {
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class RegisterClassInfo;
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class VirtRegMap;
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class LiveRegMatrix;
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class LLVM_LIBRARY_VISIBILITY AllocationOrder {
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const SmallVector<MCPhysReg, 16> Hints;
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ArrayRef<MCPhysReg> Order;
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// How far into the Order we can iterate. This is 0 if the AllocationOrder is
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// constructed with HardHints = true, Order.size() otherwise. While
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// technically a size_t, it will participate in comparisons with the
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// Iterator's Pos, which must be signed, so it's typed here as signed, too, to
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// avoid warnings and under the assumption that the size of Order is
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// relatively small.
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// IterationLimit defines an invalid iterator position.
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const int IterationLimit;
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public:
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/// Forward iterator for an AllocationOrder.
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class Iterator final {
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const AllocationOrder &AO;
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int Pos = 0;
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public:
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Iterator(const AllocationOrder &AO, int Pos) : AO(AO), Pos(Pos) {}
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/// Return true if the curent position is that of a preferred register.
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bool isHint() const { return Pos < 0; }
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/// Return the next physical register in the allocation order.
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MCRegister operator*() const {
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if (Pos < 0)
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return AO.Hints.end()[Pos];
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assert(Pos < AO.IterationLimit);
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return AO.Order[Pos];
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}
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/// Advance the iterator to the next position. If that's past the Hints
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/// list, advance to the first value that's not also in the Hints list.
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Iterator &operator++() {
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if (Pos < AO.IterationLimit)
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++Pos;
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while (Pos >= 0 && Pos < AO.IterationLimit && AO.isHint(AO.Order[Pos]))
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++Pos;
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return *this;
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}
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bool operator==(const Iterator &Other) const {
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assert(&AO == &Other.AO);
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return Pos == Other.Pos;
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}
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bool operator!=(const Iterator &Other) const { return !(*this == Other); }
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};
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/// Create a new AllocationOrder for VirtReg.
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/// @param VirtReg Virtual register to allocate for.
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/// @param VRM Virtual register map for function.
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/// @param RegClassInfo Information about reserved and allocatable registers.
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static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM,
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const RegisterClassInfo &RegClassInfo,
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const LiveRegMatrix *Matrix);
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/// Create an AllocationOrder given the Hits, Order, and HardHits values.
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/// Use the create method above - the ctor is for unittests.
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AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order,
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bool HardHints)
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: Hints(std::move(Hints)), Order(Order),
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IterationLimit(HardHints ? 0 : static_cast<int>(Order.size())) {}
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Iterator begin() const {
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return Iterator(*this, -(static_cast<int>(Hints.size())));
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}
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Iterator end() const { return Iterator(*this, IterationLimit); }
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Iterator getOrderLimitEnd(unsigned OrderLimit) const {
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assert(OrderLimit <= Order.size());
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if (OrderLimit == 0)
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return end();
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Iterator Ret(*this,
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std::min(static_cast<int>(OrderLimit) - 1, IterationLimit));
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return ++Ret;
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}
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/// Get the allocation order without reordered hints.
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ArrayRef<MCPhysReg> getOrder() const { return Order; }
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/// Return true if PhysReg is a preferred register.
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bool isHint(unsigned PhysReg) const { return is_contained(Hints, PhysReg); }
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};
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} // end namespace llvm
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#endif
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