forked from OSchip/llvm-project
62 lines
1.5 KiB
LLVM
62 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple thumbv7-eabi | FileCheck %s -check-prefix=T2
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; RUN: llc < %s -mtriple thumbv6m-eabi | FileCheck %s -check-prefix=T1
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; <rdar://problem/7569620>
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define i32 @compare_i_gt(i32 %a) {
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; T2-LABEL: compare_i_gt:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: movs r1, #24
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; T2-NEXT: cmn.w r0, #78
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; T2-NEXT: it gt
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; T2-NEXT: movgt r1, #42
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; T2-NEXT: mov r0, r1
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; T2-NEXT: bx lr
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;
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; T1-LABEL: compare_i_gt:
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; T1: @ %bb.0: @ %entry
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; T1-NEXT: mov r1, r0
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; T1-NEXT: movs r0, #77
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; T1-NEXT: mvns r3, r0
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; T1-NEXT: movs r0, #42
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; T1-NEXT: movs r2, #24
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; T1-NEXT: cmp r1, r3
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; T1-NEXT: bgt .LBB0_2
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; T1-NEXT: @ %bb.1: @ %entry
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; T1-NEXT: mov r0, r2
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; T1-NEXT: .LBB0_2: @ %entry
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; T1-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, -78
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%ret = select i1 %cmp, i32 42, i32 24
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ret i32 %ret
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}
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define i32 @compare_r_eq(i32 %a, i32 %b) {
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; T2-LABEL: compare_r_eq:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: movs r2, #24
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; T2-NEXT: cmn r0, r1
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; T2-NEXT: it eq
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; T2-NEXT: moveq r2, #42
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; T2-NEXT: mov r0, r2
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; T2-NEXT: bx lr
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;
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; T1-LABEL: compare_r_eq:
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; T1: @ %bb.0: @ %entry
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; T1-NEXT: mov r2, r0
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; T1-NEXT: movs r0, #42
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; T1-NEXT: movs r3, #24
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; T1-NEXT: cmn r2, r1
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; T1-NEXT: beq .LBB1_2
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; T1-NEXT: @ %bb.1: @ %entry
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; T1-NEXT: mov r0, r3
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; T1-NEXT: .LBB1_2: @ %entry
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; T1-NEXT: bx lr
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entry:
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%sub = sub nsw i32 0, %b
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%cmp = icmp eq i32 %a, %sub
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%ret = select i1 %cmp, i32 42, i32 24
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ret i32 %ret
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}
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