forked from OSchip/llvm-project
243 lines
6.6 KiB
Plaintext
243 lines
6.6 KiB
Plaintext
TODO:
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* gpr0 allocation
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* implement do-loop -> bdnz transform
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* implement powerpc-64 for darwin
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* use stfiwx in float->int
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* be able to combine sequences like the following into 2 instructions:
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lis r2, ha16(l2__ZTV4Cell)
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la r2, lo16(l2__ZTV4Cell)(r2)
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addi r2, r2, 8
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* Teach LLVM how to codegen this:
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unsigned short foo(float a) { return a; }
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as:
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_foo:
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fctiwz f0,f1
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stfd f0,-8(r1)
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lhz r3,-2(r1)
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blr
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not:
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_foo:
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fctiwz f0, f1
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stfd f0, -8(r1)
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lwz r2, -4(r1)
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rlwinm r3, r2, 0, 16, 31
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blr
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and:
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extern int X, Y; int* test(int C) { return C? &X : &Y; }
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as one load when using --enable-pic.
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* Support 'update' load/store instructions. These are cracked on the G5, but
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are still a codesize win.
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* Add a custom legalizer for the GlobalAddress node, to move the funky darwin
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stub stuff from the instruction selector to the legalizer (exposing low-level
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operations to the dag for optzn. For example, we want to codegen this:
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int A = 0;
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void B() { A++; }
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as:
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lis r9,ha16(_A)
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lwz r2,lo16(_A)(r9)
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addi r2,r2,1
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stw r2,lo16(_A)(r9)
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not:
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lis r2, ha16(_A)
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lwz r2, lo16(_A)(r2)
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addi r2, r2, 1
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lis r3, ha16(_A)
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stw r2, lo16(_A)(r3)
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* should hint to the branch select pass that it doesn't need to print the
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second unconditional branch, so we don't end up with things like:
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b .LBBl42__2E_expand_function_8_674 ; loopentry.24
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b .LBBl42__2E_expand_function_8_42 ; NewDefault
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b .LBBl42__2E_expand_function_8_42 ; NewDefault
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===-------------------------------------------------------------------------===
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* Codegen this:
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void test2(int X) {
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if (X == 0x12345678) bar();
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}
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as:
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xoris r0,r3,0x1234
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cmpwi cr0,r0,0x5678
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beq cr0,L6
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not:
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lis r2, 4660
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ori r2, r2, 22136
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cmpw cr0, r3, r2
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bne .LBB_test2_2
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===-------------------------------------------------------------------------===
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Lump the constant pool for each function into ONE pic object, and reference
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pieces of it as offsets from the start. For functions like this (contrived
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to have lots of constants obviously):
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double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
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We generate:
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_X:
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lis r2, ha16(.CPI_X_0)
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lfd f0, lo16(.CPI_X_0)(r2)
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lis r2, ha16(.CPI_X_1)
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lfd f2, lo16(.CPI_X_1)(r2)
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fmadd f0, f1, f0, f2
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lis r2, ha16(.CPI_X_2)
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lfd f1, lo16(.CPI_X_2)(r2)
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lis r2, ha16(.CPI_X_3)
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lfd f2, lo16(.CPI_X_3)(r2)
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fmadd f1, f0, f1, f2
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blr
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It would be better to materialize .CPI_X into a register, then use immediates
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off of the register to avoid the lis's. This is even more important in PIC
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mode.
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===-------------------------------------------------------------------------===
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Implement Newton-Rhapson method for improving estimate instructions to the
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correct accuracy, and implementing divide as multiply by reciprocal when it has
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more than one use. Itanium will want this too.
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===-------------------------------------------------------------------------===
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int foo(int a, int b) { return a == b ? 16 : 0; }
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_foo:
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cmpw cr7, r3, r4
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mfcr r2
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rlwinm r2, r2, 31, 31, 31
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slwi r3, r2, 4
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blr
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If we exposed the srl & mask ops after the MFCR that we are doing to select
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the correct CR bit, then we could fold the slwi into the rlwinm before it.
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===-------------------------------------------------------------------------===
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#define ARRAY_LENGTH 16
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union bitfield {
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struct {
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#ifndef __ppc__
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unsigned int field0 : 6;
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unsigned int field1 : 6;
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unsigned int field2 : 6;
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unsigned int field3 : 6;
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unsigned int field4 : 3;
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unsigned int field5 : 4;
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unsigned int field6 : 1;
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#else
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unsigned int field6 : 1;
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unsigned int field5 : 4;
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unsigned int field4 : 3;
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unsigned int field3 : 6;
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unsigned int field2 : 6;
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unsigned int field1 : 6;
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unsigned int field0 : 6;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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typedef struct program_t {
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union bitfield array[ARRAY_LENGTH];
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int size;
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int loaded;
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} program;
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void AdjustBitfields(program* prog, unsigned int fmt1)
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{
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unsigned int shift = 0;
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unsigned int texCount = 0;
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unsigned int i;
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for (i = 0; i < 8; i++)
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{
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prog->array[i].bitfields.field0 = texCount;
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prog->array[i].bitfields.field1 = texCount + 1;
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prog->array[i].bitfields.field2 = texCount + 2;
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prog->array[i].bitfields.field3 = texCount + 3;
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texCount += (fmt1 >> shift) & 0x7;
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shift += 3;
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}
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}
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In the loop above, the bitfield adds get generated as
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(add (shl bitfield, C1), (shl C2, C1)) where C2 is 1, 2 or 3.
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Since the input to the (or and, and) is an (add) rather than a (shl), the shift
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doesn't get folded into the rlwimi instruction. We should ideally see through
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things like this, rather than forcing llvm to generate the equivalent
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(shl (add bitfield, C2), C1) with some kind of mask.
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===-------------------------------------------------------------------------===
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Compile this (standard bitfield insert of a constant):
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void %test(uint* %tmp1) {
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%tmp2 = load uint* %tmp1 ; <uint> [#uses=1]
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%tmp5 = or uint %tmp2, 257949696 ; <uint> [#uses=1]
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%tmp6 = and uint %tmp5, 4018143231 ; <uint> [#uses=1]
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store uint %tmp6, uint* %tmp1
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ret void
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}
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to:
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_test:
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lwz r0,0(r3)
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li r2,123
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rlwimi r0,r2,21,3,10
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stw r0,0(r3)
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blr
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instead of:
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_test:
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lis r2, -4225
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lwz r4, 0(r3)
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ori r2, r2, 65535
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oris r4, r4, 3936
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and r2, r4, r2
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stw r2, 0(r3)
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blr
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===-------------------------------------------------------------------------===
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Compile this:
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int %f1(int %a, int %b) {
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%tmp.1 = and int %a, 15 ; <int> [#uses=1]
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%tmp.3 = and int %b, 240 ; <int> [#uses=1]
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%tmp.4 = or int %tmp.3, %tmp.1 ; <int> [#uses=1]
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ret int %tmp.4
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}
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without a copy. We make this currently:
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_f1:
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rlwinm r2, r4, 0, 24, 27
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rlwimi r2, r3, 0, 28, 31
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or r3, r2, r2
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blr
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The two-addr pass or RA needs to learn when it is profitable to commute an
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instruction to avoid a copy AFTER the 2-addr instruction. The 2-addr pass
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currently only commutes to avoid inserting a copy BEFORE the two addr instr.
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