forked from OSchip/llvm-project
223 lines
12 KiB
TableGen
223 lines
12 KiB
TableGen
//===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the sign and zero extension operations.
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//
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0 in {
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let Defs = [AX], Uses = [AL] in // AX = signext(AL)
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def CBW : I<0x98, RawFrm, (outs), (ins),
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"{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>;
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let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)
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def CWDE : I<0x98, RawFrm, (outs), (ins),
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"{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
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let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
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def CDQE : RI<0x98, RawFrm, (outs), (ins),
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"{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
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// FIXME: CWD/CDQ/CQO shouldn't Def the A register, but the fast register
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// allocator crashes if you remove it.
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let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
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def CWD : I<0x99, RawFrm, (outs), (ins),
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"{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
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let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
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def CDQ : I<0x99, RawFrm, (outs), (ins),
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"{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
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let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
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def CQO : RI<0x99, RawFrm, (outs), (ins),
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"{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
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}
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// Sign/Zero extenders
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let hasSideEffects = 0 in {
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def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
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"movs{bw|x}\t{$src, $dst|$dst, $src}", []>,
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TB, OpSize16, Sched<[WriteALU]>;
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let mayLoad = 1 in
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def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
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"movs{bw|x}\t{$src, $dst|$dst, $src}", []>,
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TB, OpSize16, Sched<[WriteALULd]>;
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} // hasSideEffects = 0
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def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sext GR8:$src))]>, TB,
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OpSize32, Sched<[WriteALU]>;
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def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB,
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OpSize32, Sched<[WriteALULd]>;
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def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
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"movs{wl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sext GR16:$src))]>, TB,
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OpSize32, Sched<[WriteALU]>;
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def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
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"movs{wl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sextloadi32i16 addr:$src))]>,
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OpSize32, TB, Sched<[WriteALULd]>;
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let hasSideEffects = 0 in {
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def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
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"movz{bw|x}\t{$src, $dst|$dst, $src}", []>,
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TB, OpSize16, Sched<[WriteALU]>;
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let mayLoad = 1 in
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def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
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"movz{bw|x}\t{$src, $dst|$dst, $src}", []>,
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TB, OpSize16, Sched<[WriteALULd]>;
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} // hasSideEffects = 0
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def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zext GR8:$src))]>, TB,
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OpSize32, Sched<[WriteALU]>;
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def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB,
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OpSize32, Sched<[WriteALULd]>;
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def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
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"movz{wl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zext GR16:$src))]>, TB,
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OpSize32, Sched<[WriteALU]>;
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def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
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"movz{wl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zextloadi32i16 addr:$src))]>,
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TB, OpSize32, Sched<[WriteALULd]>;
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// These instructions exist as a consequence of operand size prefix having
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// control of the destination size, but not the input size. Only support them
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// for the disassembler.
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
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def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"movs{ww|x}\t{$src, $dst|$dst, $src}",
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[]>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable;
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def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"movz{ww|x}\t{$src, $dst|$dst, $src}",
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[]>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable;
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let mayLoad = 1 in {
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def MOVSX16rm16: I<0xBF, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"movs{ww|x}\t{$src, $dst|$dst, $src}",
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[]>, OpSize16, TB, Sched<[WriteALULd]>, NotMemoryFoldable;
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def MOVZX16rm16: I<0xB7, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"movz{ww|x}\t{$src, $dst|$dst, $src}",
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[]>, TB, OpSize16, Sched<[WriteALULd]>, NotMemoryFoldable;
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} // mayLoad = 1
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} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0
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// These are the same as the regular MOVZX32rr8 and MOVZX32rm8
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// except that they use GR32_NOREX for the output operand register class
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// instead of GR32. This allows them to operate on h registers on x86-64.
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let hasSideEffects = 0, isCodeGenOnly = 1 in {
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def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg,
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(outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[]>, TB, OpSize32, Sched<[WriteALU]>;
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let mayLoad = 1 in
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def MOVZX32rm8_NOREX : I<0xB6, MRMSrcMem,
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(outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[]>, TB, OpSize32, Sched<[WriteALULd]>;
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def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg,
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(outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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[]>, TB, OpSize32, Sched<[WriteALU]>;
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let mayLoad = 1 in
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def MOVSX32rm8_NOREX : I<0xBE, MRMSrcMem,
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(outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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[]>, TB, OpSize32, Sched<[WriteALULd]>;
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}
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// MOVSX64rr8 always has a REX prefix and it has an 8-bit register
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// operand, which makes it a rare instruction with an 8-bit register
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// operand that can never access an h register. If support for h registers
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// were generalized, this would require a special register class.
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def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
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"movs{bq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR8:$src))]>, TB,
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Sched<[WriteALU]>;
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def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
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"movs{bq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i8 addr:$src))]>,
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TB, Sched<[WriteALULd]>;
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def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
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"movs{wq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR16:$src))]>, TB,
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Sched<[WriteALU]>;
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def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"movs{wq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i16 addr:$src))]>,
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TB, Sched<[WriteALULd]>;
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def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR32:$src))]>,
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Sched<[WriteALU]>, Requires<[In64BitMode]>;
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def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i32 addr:$src))]>,
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Sched<[WriteALULd]>, Requires<[In64BitMode]>;
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// These instructions exist as a consequence of operand size prefix having
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// control of the destination size, but not the input size. Only support them
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// for the disassembler.
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
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def MOVSX16rr32: I<0x63, MRMSrcReg, (outs GR16:$dst), (ins GR32:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}", []>,
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Sched<[WriteALU]>, OpSize16, Requires<[In64BitMode]>;
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def MOVSX32rr32: I<0x63, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}", []>,
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Sched<[WriteALU]>, OpSize32, Requires<[In64BitMode]>;
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let mayLoad = 1 in {
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def MOVSX16rm32: I<0x63, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}", []>,
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Sched<[WriteALULd]>, OpSize16, Requires<[In64BitMode]>;
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def MOVSX32rm32: I<0x63, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}", []>,
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Sched<[WriteALULd]>, OpSize32, Requires<[In64BitMode]>;
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} // mayLoad = 1
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} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0
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// movzbq and movzwq encodings for the disassembler
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let hasSideEffects = 0 in {
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def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
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"movz{bq|x}\t{$src, $dst|$dst, $src}", []>,
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TB, Sched<[WriteALU]>;
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let mayLoad = 1 in
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def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
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"movz{bq|x}\t{$src, $dst|$dst, $src}", []>,
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TB, Sched<[WriteALULd]>;
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def MOVZX64rr16 : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
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"movz{wq|x}\t{$src, $dst|$dst, $src}", []>,
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TB, Sched<[WriteALU]>;
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let mayLoad = 1 in
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def MOVZX64rm16 : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"movz{wq|x}\t{$src, $dst|$dst, $src}", []>,
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TB, Sched<[WriteALULd]>;
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}
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// 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a
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// 32-bit register.
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def : Pat<(i64 (zext GR8:$src)),
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(SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;
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def : Pat<(zextloadi64i8 addr:$src),
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(SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
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def : Pat<(i64 (zext GR16:$src)),
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(SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;
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def : Pat<(zextloadi64i16 addr:$src),
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(SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
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// The preferred way to do 32-bit-to-64-bit zero extension on x86-64 is to use a
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// SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible
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// when the 32-bit value is defined by a truncate or is copied from something
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// where the high bits aren't necessarily all zero. In such cases, we fall back
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// to these explicit zext instructions.
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def : Pat<(i64 (zext GR32:$src)),
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(SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;
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def : Pat<(i64 (zextloadi64i32 addr:$src)),
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(SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
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