forked from OSchip/llvm-project
174 lines
7.9 KiB
LLVM
174 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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; For this test we used to optimize the <i1 true, i1 false, i1 false, i1 true>
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; mask into <i32 2147483648, i32 0, i32 0, i32 2147483648> because we thought
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; we would lower that into a blend where only the high bit is relevant.
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; However, since the whole mask is constant, this is simplified incorrectly
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; by the generic code, because it was expecting -1 in place of 2147483648.
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;
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; The problem does not occur without AVX, because vselect of v4i32 is not legal
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; nor custom.
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;
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; <rdar://problem/18675020>
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define void @test(<4 x i16>* %a, <4 x i16>* %b) {
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; AVX-LABEL: test:
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; AVX: ## BB#0: ## %body
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; AVX-NEXT: movq {{.*}}(%rip), %rax
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; AVX-NEXT: movq %rax, (%rdi)
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; AVX-NEXT: movq {{.*}}(%rip), %rax
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; AVX-NEXT: movq %rax, (%rsi)
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; AVX-NEXT: retq
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body:
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%predphi = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> <i16 -3, i16 545, i16 4385, i16 14807>, <4 x i16> <i16 123, i16 124, i16 125, i16 127>
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%predphi42 = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> zeroinitializer
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store <4 x i16> %predphi, <4 x i16>* %a, align 8
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store <4 x i16> %predphi42, <4 x i16>* %b, align 8
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ret void
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}
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; Improve code coverage.
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;
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; When shrinking the condition used into the select to match a blend, this
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; test case exercises the path where the modified node is not the root
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; of the condition.
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define void @test2(double** %call1559, i64 %indvars.iv4198, <4 x i1> %tmp1895) {
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; AVX1-LABEL: test2:
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; AVX1: ## BB#0: ## %bb
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; AVX1-NEXT: vpslld $31, %xmm0, %xmm0
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: movq (%rdi,%rsi,8), %rax
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; AVX1-NEXT: vmovapd {{.*#+}} ymm1 = [5.000000e-01,5.000000e-01,5.000000e-01,5.000000e-01]
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; AVX1-NEXT: vblendvpd %ymm0, {{.*}}(%rip), %ymm1, %ymm0
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; AVX1-NEXT: vmovupd %ymm0, (%rax)
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test2:
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; AVX2: ## BB#0: ## %bb
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; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
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; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
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; AVX2-NEXT: movq (%rdi,%rsi,8), %rax
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; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm1 = [-0.5,-0.5,-0.5,-0.5]
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; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [0.5,0.5,0.5,0.5]
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; AVX2-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
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; AVX2-NEXT: vmovupd %ymm0, (%rax)
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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bb:
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%arrayidx1928 = getelementptr inbounds double*, double** %call1559, i64 %indvars.iv4198
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%tmp1888 = load double*, double** %arrayidx1928, align 8
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%predphi.v.v = select <4 x i1> %tmp1895, <4 x double> <double -5.000000e-01, double -5.000000e-01, double -5.000000e-01, double -5.000000e-01>, <4 x double> <double 5.000000e-01, double 5.000000e-01, double 5.000000e-01, double 5.000000e-01>
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%tmp1900 = bitcast double* %tmp1888 to <4 x double>*
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store <4 x double> %predphi.v.v, <4 x double>* %tmp1900, align 8
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ret void
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}
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; For this test, we used to optimized the conditional mask for the blend, i.e.,
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; we shrunk some of its bits.
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; However, this same mask was used in another select (%predphi31) that turned out
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; to be optimized into a and. In that case, the conditional mask was wrong.
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;
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; Make sure that the and is fed by the original mask.
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;
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; <rdar://problem/18819506>
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define void @test3(<4 x i32> %induction30, <4 x i16>* %tmp16, <4 x i16>* %tmp17, <4 x i16> %tmp3, <4 x i16> %tmp12) {
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; AVX1-LABEL: test3:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1431655766,1431655766,1431655766,1431655766]
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; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
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; AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
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; AVX1-NEXT: vpmuldq %xmm4, %xmm5, %xmm4
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; AVX1-NEXT: vpmuldq %xmm3, %xmm0, %xmm3
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; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3],xmm3[4,5],xmm4[6,7]
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; AVX1-NEXT: vpsrld $31, %xmm3, %xmm4
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; AVX1-NEXT: vpaddd %xmm4, %xmm3, %xmm3
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; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm3, %xmm3
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; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0
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; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vmovq %xmm0, (%rdi)
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; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm0
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; AVX1-NEXT: vmovq %xmm0, (%rsi)
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test3:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [1431655766,1431655766,1431655766,1431655766]
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; AVX2-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
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; AVX2-NEXT: vpshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
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; AVX2-NEXT: vpmuldq %xmm4, %xmm5, %xmm4
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; AVX2-NEXT: vpmuldq %xmm3, %xmm0, %xmm3
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; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
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; AVX2-NEXT: vpblendd {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2],xmm4[3]
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; AVX2-NEXT: vpsrld $31, %xmm3, %xmm4
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; AVX2-NEXT: vpaddd %xmm4, %xmm3, %xmm3
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm4 = [3,3,3,3]
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; AVX2-NEXT: vpmulld %xmm4, %xmm3, %xmm3
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; AVX2-NEXT: vpsubd %xmm3, %xmm0, %xmm0
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; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX2-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0
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; AVX2-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
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; AVX2-NEXT: vmovq %xmm0, (%rdi)
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; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm0
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; AVX2-NEXT: vmovq %xmm0, (%rsi)
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; AVX2-NEXT: retq
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%tmp6 = srem <4 x i32> %induction30, <i32 3, i32 3, i32 3, i32 3>
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%tmp7 = icmp eq <4 x i32> %tmp6, zeroinitializer
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%predphi = select <4 x i1> %tmp7, <4 x i16> %tmp3, <4 x i16> %tmp12
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%predphi31 = select <4 x i1> %tmp7, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> zeroinitializer
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store <4 x i16> %predphi31, <4 x i16>* %tmp16, align 8
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store <4 x i16> %predphi, <4 x i16>* %tmp17, align 8
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ret void
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}
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; We shouldn't try to lower this directly using VSELECT because we don't have
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; vpblendvb in AVX1, only in AVX2. Instead, it should be expanded.
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define <32 x i8> @PR22706(<32 x i1> %x) {
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; AVX1-LABEL: PR22706:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpsllw $7, %xmm1, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
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; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpcmpgtb %xmm1, %xmm3, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2]
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; AVX1-NEXT: vpaddb %xmm4, %xmm1, %xmm1
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; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0
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; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vpcmpgtb %xmm0, %xmm3, %xmm0
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; AVX1-NEXT: vpaddb %xmm4, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: PR22706:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vpsllw $7, %ymm0, %ymm0
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; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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%tmp = select <32 x i1> %x, <32 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <32 x i8> <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
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ret <32 x i8> %tmp
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}
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