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llvm-project/llvm/test/tools/llvm-mca/X86
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Andrea Di Biagio c2493ce4a4 [MCA][Scheduler] Improved critical memory dependency computation. 
This fixes a problem where back-pressure increases caused by register
dependencies were not correctly notified if execution was also delayed by memory
dependencies.

llvm-svn: 361740
 		2019-05-26 19:50:31 +00:00
..
Atom [X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing. 2019-05-06 21:39:51 +00:00
BdVer2 [X86] AMD Piledriver (BdVer2): major cleanup (mainly inverse throughput) 2019-05-09 13:54:51 +00:00
Broadwell [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms 2019-05-25 04:47:49 +00:00
BtVer2 [MCA][Scheduler] Improved critical memory dependency computation. 2019-05-26 19:50:31 +00:00
Generic [X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing. 2019-05-06 21:39:51 +00:00
Haswell [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms 2019-05-25 04:47:49 +00:00
SLM [X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing. 2019-05-06 21:39:51 +00:00
SandyBridge [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms 2019-05-25 04:47:49 +00:00
SkylakeClient [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms 2019-05-25 04:47:49 +00:00
SkylakeServer [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms 2019-05-25 04:47:49 +00:00
Znver1 [X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing. 2019-05-06 21:39:51 +00:00
bextr-read-after-ld.s [X86] AMD Piledriver (BdVer2): major cleanup (mainly inverse throughput) 2019-05-09 13:54:51 +00:00
bzhi-read-after-ld.s [utils] Ensure that update_mca_test_checks.py writes prefixes in alphabetical order 2018-10-04 14:42:19 +00:00
cpus.s [X86] AMD Piledriver (BdVer2): major cleanup (mainly inverse throughput) 2019-05-09 13:54:51 +00:00
default-iterations.s [llvm-mca] Add fields "Total uOps" and "uOps Per Cycle" to the report generated by the SummaryView. 2018-08-29 17:56:39 +00:00
dispatch_width.s [llvm-mca] Add fields "Total uOps" and "uOps Per Cycle" to the report generated by the SummaryView. 2018-08-29 17:56:39 +00:00
fma3-read-after-ld-1.s [utils] Ensure that update_mca_test_checks.py writes prefixes in alphabetical order 2018-10-04 14:42:19 +00:00
fma3-read-after-ld-2.s [utils] Ensure that update_mca_test_checks.py writes prefixes in alphabetical order 2018-10-04 14:42:19 +00:00
in-order-cpu.s Replace unused output filenames with /dev/null in tests 2018-07-02 18:16:44 +00:00
intel-syntax.s [MC] Separate masm integer literal lexer support from inline asm 2018-10-24 20:23:57 +00:00
invalid-assembly-sequence.s [llvm-mca] Make sure not to end the test files with an empty line. 2018-06-04 11:48:46 +00:00
invalid-cpu.s Replace unused output filenames with /dev/null in tests 2018-07-02 18:16:44 +00:00
invalid-empty-file.s Replace unused output filenames with /dev/null in tests 2018-07-02 18:16:44 +00:00
lit.local.cfg
…
llvm-mca-markers-1.s [llvm-mca] Make sure not to end the test files with an empty line. 2018-06-04 11:48:46 +00:00
llvm-mca-markers-2.s [MCA] Don't add a name to the default code region. 2019-05-08 11:00:43 +00:00
llvm-mca-markers-3.s [llvm-mca] Add fields "Total uOps" and "uOps Per Cycle" to the report generated by the SummaryView. 2018-08-29 17:56:39 +00:00
llvm-mca-markers-4.s [llvm-mca] Add fields "Total uOps" and "uOps Per Cycle" to the report generated by the SummaryView. 2018-08-29 17:56:39 +00:00
llvm-mca-markers-5.s [llvm-mca] Add fields "Total uOps" and "uOps Per Cycle" to the report generated by the SummaryView. 2018-08-29 17:56:39 +00:00
llvm-mca-markers-6.s [MCA] Add support for nested and overlapping region markers 2019-05-09 15:18:09 +00:00
llvm-mca-markers-7.s [MCA] Add support for nested and overlapping region markers 2019-05-09 15:18:09 +00:00
llvm-mca-markers-8.s [MCA] Add support for nested and overlapping region markers 2019-05-09 15:18:09 +00:00
llvm-mca-markers-9.s [MCA] Add support for nested and overlapping region markers 2019-05-09 15:18:09 +00:00
llvm-mca-markers-10.s [MCA] Add support for nested and overlapping region markers 2019-05-09 15:18:09 +00:00
llvm-mca-markers-11.s [MCA] Add support for nested and overlapping region markers 2019-05-09 15:18:09 +00:00
llvm-mca-markers-12.s [MCA] Add support for nested and overlapping region markers 2019-05-09 15:18:09 +00:00
no-sched-model.s [llvm-mca] Make sure not to end the test files with an empty line. 2018-06-04 11:48:46 +00:00
option-all-stats-1.s [llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI 2019-04-08 16:05:54 +00:00
option-all-stats-2.s [llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI 2019-04-08 16:05:54 +00:00
option-all-views-1.s [llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI 2019-04-08 16:05:54 +00:00
option-all-views-2.s [llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI 2019-04-08 16:05:54 +00:00
option-no-stats-1.s [llvm-mca] Add fields "Total uOps" and "uOps Per Cycle" to the report generated by the SummaryView. 2018-08-29 17:56:39 +00:00
read-after-ld-1.s [X86] AMD Piledriver (BdVer2): major cleanup (mainly inverse throughput) 2019-05-09 13:54:51 +00:00
read-after-ld-2.s [X86] Fix Skylake ReadAfterLd for PADDrm etc. 2018-10-16 09:50:16 +00:00
read-after-ld-3.s [llvm-mca][x86] Add PR36951 ReadAfterLd test case 2018-10-04 16:26:56 +00:00
register-file-statistics.s [NFC][MCA][BdVer2] Add bdver2 runline into register-file-statistics.s test 2018-11-10 10:56:58 +00:00
scheduler-queue-usage.s [llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI 2019-04-08 16:05:54 +00:00
sqrt-rsqrt-rcp-memop.s AMD BdVer2 (Piledriver) Initial Scheduler model 2018-10-27 20:46:30 +00:00
uop-queue.s [MCA] Add an experimental MicroOpQueue stage. 2019-03-29 12:15:37 +00:00
variable-blend-read-after-ld-1.s [X86] AMD Piledriver (BdVer2): major cleanup (mainly inverse throughput) 2019-05-09 13:54:51 +00:00
variable-blend-read-after-ld-2.s [X86] AMD Piledriver (BdVer2): major cleanup (mainly inverse throughput) 2019-05-09 13:54:51 +00:00