forked from OSchip/llvm-project
574 lines
26 KiB
C++
574 lines
26 KiB
C++
//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
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#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86RegisterInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "X86GenInstrInfo.inc"
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namespace llvm {
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class MachineInstrBuilder;
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class X86RegisterInfo;
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class X86Subtarget;
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namespace X86 {
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// X86 specific condition code. These correspond to X86_*_COND in
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// X86InstrInfo.td. They must be kept in synch.
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enum CondCode {
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COND_A = 0,
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COND_AE = 1,
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COND_B = 2,
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COND_BE = 3,
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COND_E = 4,
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COND_G = 5,
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COND_GE = 6,
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COND_L = 7,
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COND_LE = 8,
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COND_NE = 9,
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COND_NO = 10,
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COND_NP = 11,
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COND_NS = 12,
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COND_O = 13,
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COND_P = 14,
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COND_S = 15,
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LAST_VALID_COND = COND_S,
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// Artificial condition codes. These are used by AnalyzeBranch
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// to indicate a block terminated with two conditional branches that together
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// form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
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// which can't be represented on x86 with a single condition. These
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// are never used in MachineInstrs and are inverses of one another.
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COND_NE_OR_P,
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COND_E_AND_NP,
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COND_INVALID
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};
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// Turn condition code into conditional branch opcode.
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unsigned GetCondBranchFromCond(CondCode CC);
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/// \brief Return a set opcode for the given condition and whether it has
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/// a memory operand.
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unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
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/// \brief Return a cmov opcode for the given condition, register size in
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/// bytes, and operand type.
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unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
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bool HasMemoryOperand = false);
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// Turn CMov opcode into condition code.
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CondCode getCondFromCMovOpc(unsigned Opc);
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/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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/// e.g. turning COND_E to COND_NE.
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CondCode GetOppositeBranchCondition(CondCode CC);
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} // end namespace X86;
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/// isGlobalStubReference - Return true if the specified TargetFlag operand is
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/// a reference to a stub for a global, not the global itself.
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inline static bool isGlobalStubReference(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_DLLIMPORT: // dllimport stub.
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case X86II::MO_GOTPCREL: // rip-relative GOT reference.
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case X86II::MO_GOT: // normal GOT reference.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
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return true;
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default:
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return false;
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}
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}
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/// isGlobalRelativeToPICBase - Return true if the specified global value
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/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
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/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
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inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
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case X86II::MO_GOT: // isPICStyleGOT: other global.
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case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
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case X86II::MO_TLVP: // ??? Pretty sure..
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return true;
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default:
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return false;
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}
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}
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inline static bool isScale(const MachineOperand &MO) {
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return MO.isImm() &&
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(MO.getImm() == 1 || MO.getImm() == 2 ||
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MO.getImm() == 4 || MO.getImm() == 8);
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}
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inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
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if (MI.getOperand(Op).isFI())
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return true;
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return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
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MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
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isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
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MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
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(MI.getOperand(Op + X86::AddrDisp).isImm() ||
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MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
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MI.getOperand(Op + X86::AddrDisp).isCPI() ||
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MI.getOperand(Op + X86::AddrDisp).isJTI());
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}
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inline static bool isMem(const MachineInstr &MI, unsigned Op) {
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if (MI.getOperand(Op).isFI())
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return true;
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return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
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MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
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}
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class X86InstrInfo final : public X86GenInstrInfo {
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X86Subtarget &Subtarget;
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const X86RegisterInfo RI;
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/// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
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/// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
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///
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typedef DenseMap<unsigned,
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std::pair<uint16_t, uint16_t> > RegOp2MemOpTableType;
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RegOp2MemOpTableType RegOp2MemOpTable2Addr;
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RegOp2MemOpTableType RegOp2MemOpTable0;
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RegOp2MemOpTableType RegOp2MemOpTable1;
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RegOp2MemOpTableType RegOp2MemOpTable2;
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RegOp2MemOpTableType RegOp2MemOpTable3;
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RegOp2MemOpTableType RegOp2MemOpTable4;
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/// MemOp2RegOpTable - Load / store unfolding opcode map.
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///
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typedef DenseMap<unsigned,
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std::pair<uint16_t, uint16_t> > MemOp2RegOpTableType;
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MemOp2RegOpTableType MemOp2RegOpTable;
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static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
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MemOp2RegOpTableType &M2RTable,
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uint16_t RegOp, uint16_t MemOp, uint16_t Flags);
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virtual void anchor();
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bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallVectorImpl<MachineInstr *> &CondBranches,
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bool AllowModify) const;
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public:
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explicit X86InstrInfo(X86Subtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const X86RegisterInfo &getRegisterInfo() const { return RI; }
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/// getSPAdjust - This returns the stack pointer adjustment made by
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/// this instruction. For x86, we need to handle more complex call
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/// sequences involving PUSHes.
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int getSPAdjust(const MachineInstr &MI) const override;
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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/// true, then it's expected the pre-extension value is available as a subreg
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/// of the result register. This also returns the sub-register index in
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/// SubIdx.
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bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const override;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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/// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
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int &FrameIndex) const override;
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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AliasAnalysis *AA) const override;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr &Orig,
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const TargetRegisterInfo &TRI) const override;
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/// Given an operand within a MachineInstr, insert preceding code to put it
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/// into the right format for a particular kind of LEA instruction. This may
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/// involve using an appropriate super-register instead (with an implicit use
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/// of the original) or creating a new virtual register and inserting COPY
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/// instructions to get the data into the right class.
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///
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/// Reference parameters are set to indicate how caller should add this
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/// operand to the LEA instruction.
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bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
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unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
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bool &isKill, bool &isUndef,
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MachineOperand &ImplicitOp) const;
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineInstr &MI,
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LiveVariables *LV) const override;
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/// Returns true iff the routine could find two commutable operands in the
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/// given machine instruction.
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/// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
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/// input values can be re-defined in this method only if the input values
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/// are not pre-defined, which is designated by the special value
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/// 'CommuteAnyOperandIndex' assigned to it.
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/// If both of indices are pre-defined and refer to some operands, then the
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/// method simply returns true if the corresponding operands are commutable
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/// and returns false otherwise.
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///
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/// For example, calling this method this way:
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/// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
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/// findCommutedOpIndices(MI, Op1, Op2);
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/// can be interpreted as a query asking to find an operand that would be
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/// commutable with the operand#1.
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bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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/// Returns true if the routine could find two commutable operands
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/// in the given FMA instruction. Otherwise, returns false.
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///
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/// \p SrcOpIdx1 and \p SrcOpIdx2 are INPUT and OUTPUT arguments.
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/// The output indices of the commuted operands are returned in these
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/// arguments. Also, the input values of these arguments may be preset either
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/// to indices of operands that must be commuted or be equal to a special
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/// value 'CommuteAnyOperandIndex' which means that the corresponding
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/// operand index is not set and this method is free to pick any of
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/// available commutable operands.
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///
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/// For example, calling this method this way:
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/// unsigned Idx1 = 1, Idx2 = CommuteAnyOperandIndex;
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/// findFMA3CommutedOpIndices(MI, Idx1, Idx2);
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/// can be interpreted as a query asking if the operand #1 can be swapped
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/// with any other available operand (e.g. operand #2, operand #3, etc.).
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///
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/// The returned FMA opcode may differ from the opcode in the given MI.
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/// For example, commuting the operands #1 and #3 in the following FMA
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/// FMA213 #1, #2, #3
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/// results into instruction with adjusted opcode:
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/// FMA231 #3, #2, #1
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bool findFMA3CommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const;
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/// Returns an adjusted FMA opcode that must be used in FMA instruction that
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/// performs the same computations as the given MI but which has the operands
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/// \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
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/// It may return 0 if it is unsafe to commute the operands.
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///
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/// The returned FMA opcode may differ from the opcode in the given \p MI.
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/// For example, commuting the operands #1 and #3 in the following FMA
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/// FMA213 #1, #2, #3
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/// results into instruction with adjusted opcode:
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/// FMA231 #3, #2, #1
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unsigned getFMA3OpcodeToCommuteOperands(MachineInstr &MI, unsigned SrcOpIdx1,
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unsigned SrcOpIdx2) const;
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// Branch analysis.
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bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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int64_t &Offset,
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const TargetRegisterInfo *TRI) const override;
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bool AnalyzeBranchPredicate(MachineBasicBlock &MBB,
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TargetInstrInfo::MachineBranchPredicate &MBP,
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bool AllowModify = false) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL) const override;
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bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
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unsigned, unsigned, int&, int&, int&) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, unsigned DstReg,
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ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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unsigned FalseReg) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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MachineInstr::mmo_iterator MMOBegin,
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MachineInstr::mmo_iterator MMOEnd,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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MachineInstr::mmo_iterator MMOBegin,
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MachineInstr::mmo_iterator MMOEnd,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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/// foldMemoryOperand - If this target supports it, fold a load or store of
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/// the specified stack slot into the specified machine instruction for the
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/// specified operand(s). If this is possible, the target should perform the
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/// folding and return true, otherwise it should return false. If it folds
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/// the instruction, it is likely that the MachineInstruction the iterator
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/// references has been changed.
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MachineInstr *
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
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ArrayRef<unsigned> Ops,
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MachineBasicBlock::iterator InsertPt, int FrameIndex,
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LiveIntervals *LIS = nullptr) const override;
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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MachineInstr *foldMemoryOperandImpl(
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MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
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MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
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LiveIntervals *LIS = nullptr) const override;
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/// unfoldMemoryOperand - Separate a single instruction which folded a load or
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/// a store or a load and a store into two or more instruction. If this is
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/// possible, returns true as well as the new instructions by reference.
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bool
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unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
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bool UnfoldLoad, bool UnfoldStore,
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SmallVectorImpl<MachineInstr *> &NewMIs) const override;
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bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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SmallVectorImpl<SDNode*> &NewNodes) const override;
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/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
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/// instruction after load / store are unfolded from an instruction of the
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/// specified opcode. It returns zero if the specified unfolding is not
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/// possible. If LoadRegIndex is non-null, it is filled in with the operand
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/// index of the operand which will hold the register holding the loaded
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/// value.
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unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
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bool UnfoldLoad, bool UnfoldStore,
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unsigned *LoadRegIndex = nullptr) const override;
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/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
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/// to determine if two loads are loading from the same base address. It
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/// should only return true if the base pointers are the same and the
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/// only differences between the two addresses are the offset. It also returns
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/// the offsets by reference.
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bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
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int64_t &Offset2) const override;
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/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
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/// be scheduled togther. On some targets if two loads are loading from
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/// addresses in the same cache line, it's better if they are scheduled
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/// together. This function takes two integers that represent the load offsets
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/// from the common base address. It returns true if it decides it's desirable
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/// to schedule the two loads together. "NumLoads" is the number of loads that
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/// have already been scheduled after Load1.
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bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const override;
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bool shouldScheduleAdjacent(MachineInstr &First,
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MachineInstr &Second) const override;
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void getNoopForMachoTarget(MCInst &NopInst) const override;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
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/// instruction that defines the specified register class.
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bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
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/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
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/// would clobber the EFLAGS condition register. Note the result may be
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/// conservative. If it cannot definitely determine the safety after visiting
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/// a few instructions in each direction it assumes it's not safe.
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bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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/// True if MI has a condition code def, e.g. EFLAGS, that is
|
|
/// not marked dead.
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bool hasLiveCondCodeDef(MachineInstr &MI) const;
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|
|
|
/// getGlobalBaseReg - Return a virtual register initialized with the
|
|
/// the global base register value. Output instructions required to
|
|
/// initialize the register in the function entry block, if necessary.
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|
///
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|
unsigned getGlobalBaseReg(MachineFunction *MF) const;
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|
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|
std::pair<uint16_t, uint16_t>
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|
getExecutionDomain(const MachineInstr &MI) const override;
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|
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|
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
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|
|
|
unsigned
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|
getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
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const TargetRegisterInfo *TRI) const override;
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unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
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|
const TargetRegisterInfo *TRI) const override;
|
|
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
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|
const TargetRegisterInfo *TRI) const override;
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|
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|
MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
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|
unsigned OpNum,
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|
ArrayRef<MachineOperand> MOs,
|
|
MachineBasicBlock::iterator InsertPt,
|
|
unsigned Size, unsigned Alignment,
|
|
bool AllowCommute) const;
|
|
|
|
void
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|
getUnconditionalBranch(MCInst &Branch,
|
|
const MCSymbolRefExpr *BranchTarget) const override;
|
|
|
|
void getTrap(MCInst &MI) const override;
|
|
|
|
unsigned getJumpInstrTableEntryBound() const override;
|
|
|
|
bool isHighLatencyDef(int opc) const override;
|
|
|
|
bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
|
|
const MachineRegisterInfo *MRI,
|
|
const MachineInstr &DefMI, unsigned DefIdx,
|
|
const MachineInstr &UseMI,
|
|
unsigned UseIdx) const override;
|
|
|
|
bool useMachineCombiner() const override {
|
|
return true;
|
|
}
|
|
|
|
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
|
|
|
|
bool hasReassociableOperands(const MachineInstr &Inst,
|
|
const MachineBasicBlock *MBB) const override;
|
|
|
|
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
|
|
MachineInstr &NewMI1,
|
|
MachineInstr &NewMI2) const override;
|
|
|
|
/// analyzeCompare - For a comparison instruction, return the source registers
|
|
/// in SrcReg and SrcReg2 if having two register operands, and the value it
|
|
/// compares against in CmpValue. Return true if the comparison instruction
|
|
/// can be analyzed.
|
|
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
|
|
unsigned &SrcReg2, int &CmpMask,
|
|
int &CmpValue) const override;
|
|
|
|
/// optimizeCompareInstr - Check if there exists an earlier instruction that
|
|
/// operates on the same source operands and sets flags in the same way as
|
|
/// Compare; remove Compare if possible.
|
|
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
|
|
unsigned SrcReg2, int CmpMask, int CmpValue,
|
|
const MachineRegisterInfo *MRI) const override;
|
|
|
|
/// optimizeLoadInstr - Try to remove the load by folding it to a register
|
|
/// operand at the use. We fold the load instructions if and only if the
|
|
/// def and use are in the same BB. We only look at one load and see
|
|
/// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
|
|
/// defined by the load we are trying to fold. DefMI returns the machine
|
|
/// instruction that defines FoldAsLoadDefReg, and the function returns
|
|
/// the machine instruction generated due to folding.
|
|
MachineInstr *optimizeLoadInstr(MachineInstr &MI,
|
|
const MachineRegisterInfo *MRI,
|
|
unsigned &FoldAsLoadDefReg,
|
|
MachineInstr *&DefMI) const override;
|
|
|
|
std::pair<unsigned, unsigned>
|
|
decomposeMachineOperandsTargetFlags(unsigned TF) const override;
|
|
|
|
ArrayRef<std::pair<unsigned, const char *>>
|
|
getSerializableDirectMachineOperandTargetFlags() const override;
|
|
|
|
protected:
|
|
/// Commutes the operands in the given instruction by changing the operands
|
|
/// order and/or changing the instruction's opcode and/or the immediate value
|
|
/// operand.
|
|
///
|
|
/// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
|
|
/// to be commuted.
|
|
///
|
|
/// Do not call this method for a non-commutable instruction or
|
|
/// non-commutable operands.
|
|
/// Even though the instruction is commutable, the method may still
|
|
/// fail to commute the operands, null pointer is returned in such cases.
|
|
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
|
|
unsigned CommuteOpIdx1,
|
|
unsigned CommuteOpIdx2) const override;
|
|
|
|
private:
|
|
MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
|
|
MachineFunction::iterator &MFI,
|
|
MachineInstr &MI,
|
|
LiveVariables *LV) const;
|
|
|
|
/// Handles memory folding for special case instructions, for instance those
|
|
/// requiring custom manipulation of the address.
|
|
MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
|
|
unsigned OpNum,
|
|
ArrayRef<MachineOperand> MOs,
|
|
MachineBasicBlock::iterator InsertPt,
|
|
unsigned Size, unsigned Align) const;
|
|
|
|
/// isFrameOperand - Return true and the FrameIndex if the specified
|
|
/// operand and follow operands form a reference to the stack frame.
|
|
bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
|
|
int &FrameIndex) const;
|
|
|
|
/// Expand the MOVImmSExti8 pseudo-instructions.
|
|
bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const;
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|