llvm-project/llvm/test/CodeGen
Craig Topper b1c304c494 [CodeGen] Try to make the print of memory operand alignment a little more user friendly.
Memory operands store a base alignment that does not factor in
the effect of the offset on the alignment.

Previously the printing code only printed the base alignment if
it was different than the size. If there is an offset, the reader
would need to figure out the effective alignment themselves. This
has confused me before and someone else was recently confused on
IRC.

This patch prints the possibly offset adjusted alignment if it is
different than the size. And prints the base alignment if it is
different than the alignment. The MIR parser has been updated to
read basealign in addition to align.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D94344
2021-01-11 19:58:47 -08:00
..
AArch64 [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
AMDGPU [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
ARC
ARM [NFC] Disallow unused prefixes under llvm/test/CodeGen 2021-01-11 12:32:18 -08:00
AVR
BPF [BPF] support atomic instructions 2020-12-03 07:38:00 -08:00
Generic Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
Hexagon [Hexagon] Custom-widen SETCC's operands 2021-01-11 12:21:49 -06:00
Inputs
Lanai
MIR [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
MSP430 OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
Mips [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
NVPTX [NFC] Disallow unused prefixes under llvm/test/CodeGen 2021-01-11 12:32:18 -08:00
PowerPC [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
RISCV [RISCV] Define the vfclass RVV intrinsics 2021-01-11 17:40:09 -06:00
SPARC [CodeGen][SimplifyCFG] Teach DwarfEHPrepare to preserve DomTree 2021-01-02 01:01:19 +03:00
SystemZ [SystemZ][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:26:09 -08:00
Thumb OpaquePtr: Update more tests to use typed sret 2020-11-20 20:08:43 -05:00
Thumb2 [ARM] Custom lower i1 vector truncates 2021-01-08 18:21:00 +00:00
VE [VE] Support additional VMRGW and VMV intrinsic instructions 2021-01-11 20:50:31 +09:00
WebAssembly [WebAssembly] Ensure terminate pads are a single BB 2021-01-11 17:54:28 -08:00
WinCFGuard
WinEH
X86 [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
XCore [test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:47:16 -08:00
lit.local.cfg [NFC] Disallow unused prefixes under llvm/test/CodeGen 2021-01-11 12:32:18 -08:00