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llvm-project/llvm/test/MC/Mips/micromips64r6
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Simon Dardis 273fc26b79 [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases 
Add the instruction alias sgtu (register form only), two operand forms of
s[rl]l and sra, and missing single/two operand forms of dnegu/neg.

Reviewers: dsanders

Differential Revision: https://reviews.llvm.org/D22752

llvm-svn: 276736
 		2016-07-26 09:13:46 +00:00
..
invalid-wrong-error.s [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
invalid.s [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
relocations.s ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocation 2016-05-19 12:20:40 +00:00
valid.s [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases 2016-07-26 09:13:46 +00:00