llvm-project/llvm/test/MC/Disassembler
Sjoerd Meijer 3b599d75d5 [AArch64] Armv8.4-A: Virtualization system registers
This adds the Secure EL2 extension.

Differential Revision: https://reviews.llvm.org/D48711

llvm-svn: 335962
2018-06-29 11:03:15 +00:00
..
AArch64 [AArch64] Armv8.4-A: Virtualization system registers 2018-06-29 11:03:15 +00:00
AMDGPU AMDGPU: Fix v_dot{4, 8}* instruction encoding 2018-05-15 19:32:47 +00:00
ARC [ARC] Add LImm support for J/JL 2018-04-13 15:10:34 +00:00
ARM ARM: correctly decode VFP instructions following unpredictable t2IT 2018-06-26 11:39:20 +00:00
Hexagon [Hexagon] Remove trailing spaces, NFC 2017-11-22 20:43:00 +00:00
Lanai
Mips [mips] Correct the predicates of arithmetic and logic instructions. 2018-05-30 11:33:35 +00:00
PowerPC [PowerPC] Fix incorrectly encoded wait instruction 2018-06-25 19:28:27 +00:00
Sparc
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
WebAssembly [WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. 2018-06-18 21:22:44 +00:00
X86 [X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result. 2018-06-27 19:03:36 +00:00
XCore