forked from OSchip/llvm-project
545 lines
20 KiB
TableGen
545 lines
20 KiB
TableGen
//=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
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// below is to define a generic SchedWriteRes for every combination of
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// latency and microOps. The naming conventions is to use a prefix, one field
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// for latency, and one or more microOp count/type designators.
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// Prefix: A57Write
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// Latency: #cyc
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// MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
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//
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// e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
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// 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Define Generic 1 micro-op types
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def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
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def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
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def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
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def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
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def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
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def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
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let ResourceCycles = [17]; }
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def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
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let ResourceCycles = [19]; }
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def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
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def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
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def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
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def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
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def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
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let ResourceCycles = [32]; }
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def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
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let ResourceCycles = [35]; }
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def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
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def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
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def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
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def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
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def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
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def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
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def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
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def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
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def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
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//===----------------------------------------------------------------------===//
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// Define Generic 2 micro-op types
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def A57Write_64cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
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let Latency = 64;
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let NumMicroOps = 2;
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let ResourceCycles = [32, 32];
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}
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def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
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A57UnitL]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,
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A57UnitX]> {
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let Latency = 7;
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let NumMicroOps = 2;
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}
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def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL,
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A57UnitV]> {
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let Latency = 8;
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let NumMicroOps = 2;
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}
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def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 2;
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}
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def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
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let Latency = 8;
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let NumMicroOps = 2;
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}
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def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI,
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A57UnitL]> {
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let Latency = 5;
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let NumMicroOps = 2;
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}
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def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 5;
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let NumMicroOps = 2;
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}
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def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
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let Latency = 5;
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let NumMicroOps = 2;
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}
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def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
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A57UnitV]> {
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let Latency = 10;
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let NumMicroOps = 2;
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}
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def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 10;
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let NumMicroOps = 2;
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}
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def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB,
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A57UnitI]> {
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let Latency = 1;
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let NumMicroOps = 2;
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}
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def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI,
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A57UnitS]> {
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let Latency = 1;
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let NumMicroOps = 2;
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}
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def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB,
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A57UnitI]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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def A57Write_34cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
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let Latency = 34;
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let NumMicroOps = 2;
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let ResourceCycles = [17, 17];
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}
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def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
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A57UnitM]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,
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A57UnitS]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,
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A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI,
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A57UnitL]> {
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let Latency = 4;
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let NumMicroOps = 2;
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}
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def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
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let Latency = 4;
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let NumMicroOps = 2;
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}
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//===----------------------------------------------------------------------===//
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// Define Generic 3 micro-op types
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def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
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let Latency = 10;
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let NumMicroOps = 3;
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}
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def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI,
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A57UnitS, A57UnitS]> {
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let Latency = 2;
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let NumMicroOps = 3;
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}
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def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI,
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A57UnitS,
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A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 3;
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}
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def A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM,
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A57UnitS, A57UnitS]> {
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let Latency = 3;
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let NumMicroOps = 3;
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}
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def A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> {
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let Latency = 3;
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let NumMicroOps = 3;
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}
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def A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS,
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A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 3;
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}
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def A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI,
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A57UnitL, A57UnitL]> {
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let Latency = 5;
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let NumMicroOps = 3;
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}
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def A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI,
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A57UnitL, A57UnitL]> {
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let Latency = 6;
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let NumMicroOps = 3;
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}
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def A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
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let Latency = 6;
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let NumMicroOps = 3;
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}
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def A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> {
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let Latency = 7;
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let NumMicroOps = 3;
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}
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def A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI,
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A57UnitL,
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A57UnitV]> {
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let Latency = 8;
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let NumMicroOps = 3;
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}
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def A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL,
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A57UnitV, A57UnitV]> {
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let Latency = 8;
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let NumMicroOps = 3;
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}
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def A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
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let Latency = 8;
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let NumMicroOps = 3;
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}
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def A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 3;
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}
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//===----------------------------------------------------------------------===//
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// Define Generic 4 micro-op types
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def A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,
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A57UnitS, A57UnitS]> {
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let Latency = 2;
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let NumMicroOps = 4;
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}
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def A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,
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A57UnitS, A57UnitS]> {
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let Latency = 3;
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let NumMicroOps = 4;
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}
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def A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI,
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A57UnitS, A57UnitS, A57UnitS]> {
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let Latency = 3;
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let NumMicroOps = 4;
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}
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def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI,
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A57UnitS, A57UnitS,
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A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 4;
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}
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def A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS,
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A57UnitS, A57UnitS]> {
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let Latency = 4;
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let NumMicroOps = 4;
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}
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def A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI,
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A57UnitL, A57UnitL, A57UnitL]> {
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let Latency = 7;
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let NumMicroOps = 4;
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}
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def A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI,
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A57UnitL, A57UnitL]> {
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let Latency = 5;
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let NumMicroOps = 4;
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}
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def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI,
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A57UnitL,
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A57UnitV, A57UnitV]> {
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let Latency = 8;
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let NumMicroOps = 4;
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}
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def A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL,
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A57UnitL, A57UnitL]> {
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let Latency = 8;
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let NumMicroOps = 4;
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}
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def A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL,
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A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 4;
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}
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def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL,
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A57UnitV, A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 4;
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}
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def A57Write_12cyc_4V : SchedWriteRes<[A57UnitV, A57UnitV,
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A57UnitV, A57UnitV]> {
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let Latency = 12;
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let NumMicroOps = 4;
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}
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//===----------------------------------------------------------------------===//
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// Define Generic 5 micro-op types
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def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
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A57UnitV, A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 5;
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}
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def A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI,
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A57UnitL, A57UnitL,
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A57UnitL, A57UnitL]> {
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let Latency = 8;
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let NumMicroOps = 5;
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}
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def A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI,
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A57UnitS, A57UnitS,
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A57UnitS, A57UnitS]> {
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let Latency = 4;
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let NumMicroOps = 5;
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}
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def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI,
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A57UnitL, A57UnitL,
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A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 5;
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}
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def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI,
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A57UnitL,
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A57UnitV, A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 5;
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}
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def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL,
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A57UnitV, A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 5;
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}
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def A57Write_9cyc_5V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
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A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 5;
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}
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//===----------------------------------------------------------------------===//
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// Define Generic 6 micro-op types
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def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI,
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A57UnitS, A57UnitS, A57UnitS,
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A57UnitV, A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 6;
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}
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def A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI,
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A57UnitS, A57UnitS,
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A57UnitS, A57UnitS]> {
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let Latency = 4;
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let NumMicroOps = 6;
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}
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def A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS,
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A57UnitS, A57UnitS,
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A57UnitV, A57UnitV]> {
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let Latency = 4;
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let NumMicroOps = 6;
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}
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def A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
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A57UnitS, A57UnitS, A57UnitS]> {
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let Latency = 6;
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let NumMicroOps = 6;
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}
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def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI,
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A57UnitL, A57UnitL,
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A57UnitV, A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 6;
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}
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def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI,
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A57UnitL,
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A57UnitV, A57UnitV,
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A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 6;
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}
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def A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL,
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A57UnitV, A57UnitV,
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A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 6;
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}
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//===----------------------------------------------------------------------===//
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// Define Generic 7 micro-op types
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def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL,
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A57UnitV, A57UnitV,
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A57UnitV, A57UnitV]> {
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let Latency = 10;
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let NumMicroOps = 7;
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}
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def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI,
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A57UnitS, A57UnitS,
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A57UnitS, A57UnitS,
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A57UnitV, A57UnitV]> {
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let Latency = 4;
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let NumMicroOps = 7;
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}
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def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI,
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A57UnitS, A57UnitS, A57UnitS,
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A57UnitS, A57UnitS, A57UnitS]> {
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let Latency = 6;
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let NumMicroOps = 7;
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}
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def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI,
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A57UnitL, A57UnitL,
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A57UnitV, A57UnitV,
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A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 7;
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}
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def A57Write_12cyc_7V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
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A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV]> {
|
|
let Latency = 12;
|
|
let NumMicroOps = 7;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Define Generic 8 micro-op types
|
|
|
|
def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI,
|
|
A57UnitL, A57UnitL, A57UnitL,
|
|
A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV]> {
|
|
let Latency = 10;
|
|
let NumMicroOps = 8;
|
|
}
|
|
def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL,
|
|
A57UnitL, A57UnitL,
|
|
A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV]> {
|
|
let Latency = 11;
|
|
let NumMicroOps = 8;
|
|
}
|
|
def A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS]> {
|
|
let Latency = 8;
|
|
let NumMicroOps = 8;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Define Generic 9 micro-op types
|
|
|
|
def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI,
|
|
A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS]> {
|
|
let Latency = 8;
|
|
let NumMicroOps = 9;
|
|
}
|
|
def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI,
|
|
A57UnitL, A57UnitL,
|
|
A57UnitL, A57UnitL,
|
|
A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV]> {
|
|
let Latency = 11;
|
|
let NumMicroOps = 9;
|
|
}
|
|
def A57Write_15cyc_9V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV, A57UnitV]> {
|
|
let Latency = 15;
|
|
let NumMicroOps = 9;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Define Generic 10 micro-op types
|
|
|
|
def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS, A57UnitS,
|
|
A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV]> {
|
|
let Latency = 6;
|
|
let NumMicroOps = 10;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Define Generic 11 micro-op types
|
|
|
|
def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI,
|
|
A57UnitS, A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS, A57UnitS,
|
|
A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV]> {
|
|
let Latency = 6;
|
|
let NumMicroOps = 11;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Define Generic 12 micro-op types
|
|
|
|
def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS, A57UnitS, A57UnitS,
|
|
A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV]> {
|
|
let Latency = 8;
|
|
let NumMicroOps = 12;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Define Generic 13 micro-op types
|
|
|
|
def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI,
|
|
A57UnitS, A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS, A57UnitS,
|
|
A57UnitS, A57UnitS,
|
|
A57UnitV, A57UnitV,
|
|
A57UnitV, A57UnitV]> {
|
|
let Latency = 8;
|
|
let NumMicroOps = 13;
|
|
}
|
|
|