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Tom Stellard fa8f204c5b AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklist 
Summary:
When we split SMRD instructions into two MUBUFs we were adding the users
of the newly created MUBUFs to the VALU worklist.  However, the only
users these instructions had was the REG_SEQUENCE that was inserted
by splitSMRD when the original SMRD instruction was split.

We need to make sure to add the users of the original SMRD to the VALU
worklist before it is split.

I have a test case, but it requires one other bug fix, so it will be
added in a later commt.

Reviewers: mareko, arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D17101

llvm-svn: 260588
 		2016-02-11 21:14:34 +00:00
..
AsmParser [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsing 2016-02-11 18:25:26 +00:00
InstPrinter AMDGPU: waitcnt operand fixes 2016-01-28 17:13:44 +00:00
MCTargetDesc Remove autoconf support 2016-01-26 21:29:08 +00:00
TargetInfo Remove autoconf support 2016-01-26 21:29:08 +00:00
Utils Remove autoconf support 2016-01-26 21:29:08 +00:00
AMDGPU.h AMDGPU/SI: Correctly initialize SIInsertWaits pass 2016-02-05 17:42:38 +00:00
AMDGPU.td AMDGPU: Match some med3 patterns 2016-01-28 20:53:42 +00:00
AMDGPUAlwaysInlinePass.cpp AMDGPU: Minor cleanups to always inline pass 2015-07-13 19:08:36 +00:00
AMDGPUAnnotateKernelFeatures.cpp AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptr 2016-01-30 05:10:59 +00:00
AMDGPUAnnotateUniformValues.cpp AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions 2015-12-15 20:55:55 +00:00
AMDGPUAsmPrinter.cpp AMDGPU: Set DX10Clamp bit 2016-01-28 20:53:35 +00:00
AMDGPUAsmPrinter.h AMDGPU: Emit note directive for HSA even if there are no functions 2016-01-12 17:18:17 +00:00
AMDGPUCallingConv.td AMDGPU/SI: Add support for non-void functions 2016-01-13 17:23:04 +00:00
AMDGPUFrameLowering.cpp AMDGPU: Fix old comments that mention AMDIL 2016-01-20 21:22:21 +00:00
AMDGPUFrameLowering.h AMDGPU: Create emergency stack slots during frame lowering 2015-11-06 18:17:45 +00:00
AMDGPUISelDAGToDAG.cpp Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
AMDGPUISelLowering.cpp AMDGPU: Split R600 and SI store lowering 2016-02-11 05:32:46 +00:00
AMDGPUISelLowering.h AMDGPU: Split R600 and SI store lowering 2016-02-11 05:32:46 +00:00
AMDGPUInstrInfo.cpp AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cpp 2016-01-28 16:04:37 +00:00
AMDGPUInstrInfo.h AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfo 2016-02-05 18:44:57 +00:00
AMDGPUInstrInfo.td AMDGPU: Match some med3 patterns 2016-01-28 20:53:42 +00:00
AMDGPUInstructions.td AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
AMDGPUIntrinsicInfo.cpp [llvm-tblgen] Avoid StringMatcher for GCC and MS builtin names 2016-01-27 01:43:12 +00:00
AMDGPUIntrinsicInfo.h
…
AMDGPUIntrinsics.td AMDGPU: Remove bfi and bfm intrinsics 2016-02-08 19:06:01 +00:00
AMDGPUMCInstLower.cpp AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI 2015-12-21 18:44:27 +00:00
AMDGPUMCInstLower.h
…
AMDGPUMachineFunction.cpp AMDGPU/SI: Add getShaderType() function to Utils/ 2015-12-15 16:26:16 +00:00
AMDGPUMachineFunction.h AMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU_HSA_KERNEL 2015-11-06 11:45:14 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp AMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowering pass 2015-10-01 21:16:05 +00:00
AMDGPUPromoteAlloca.cpp AMDGPU: Preserve alignments on new created globals 2016-02-05 19:47:23 +00:00
AMDGPURegisterInfo.cpp
…
AMDGPURegisterInfo.h AMDGPU: Remove dead code 2015-09-19 06:41:10 +00:00
AMDGPURegisterInfo.td AMDGPU: Set SubRegIndex size and offset 2015-07-30 17:03:11 +00:00
AMDGPUSubtarget.cpp AMDGPU: Match some med3 patterns 2016-01-28 20:53:42 +00:00
AMDGPUSubtarget.h AMDGPU: Match some med3 patterns 2016-01-28 20:53:42 +00:00
AMDGPUTargetMachine.cpp AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors 2016-02-05 18:29:17 +00:00
AMDGPUTargetMachine.h AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors 2016-02-05 18:29:17 +00:00
AMDGPUTargetObjectFile.cpp AMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA 2015-12-15 22:39:36 +00:00
AMDGPUTargetObjectFile.h AMDGPU/SI: Emit constant arrays in the .text section 2015-12-10 02:13:01 +00:00
AMDGPUTargetTransformInfo.cpp AMDGPU: Fix not handling new workitem intrinsics in DivergenceAnalysis 2016-02-11 05:32:51 +00:00
AMDGPUTargetTransformInfo.h AMDGPU: Override getCFInstrCost 2015-12-16 18:37:19 +00:00
AMDILCFGStructurizer.cpp Normalize MBB's successors' probabilities in several locations. 2015-12-13 09:26:17 +00:00
AMDKernelCodeT.h AMDGPU/SI: Update amd_kernel_code_t definition and add assembler support 2015-06-26 21:58:31 +00:00
CIInstructions.td AMDGPU: Tidy minor td file issues 2016-01-26 04:49:22 +00:00
CMakeLists.txt Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
CaymanInstructions.td AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
EvergreenInstructions.td AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
LLVMBuild.txt AMDGPU: Fix old comments that mention AMDIL 2016-01-20 21:22:21 +00:00
Processors.td AMDGPU/SI: Stoney has only 16 LDS banks 2016-01-27 11:19:45 +00:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp Update to use new name alignTo(). 2016-01-14 21:06:47 +00:00
R600Defines.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
…
R600ISelLowering.cpp AMDGPU: Split R600 and SI store lowering 2016-02-11 05:32:46 +00:00
R600ISelLowering.h AMDGPU: Split R600 and SI store lowering 2016-02-11 05:32:46 +00:00
R600InstrFormats.td
…
R600InstrInfo.cpp AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfo 2016-02-05 18:44:57 +00:00
R600InstrInfo.h AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfo 2016-02-05 18:44:57 +00:00
R600Instructions.td AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
R600Intrinsics.td AMDGPU: Move AMDGPU intrinsics only used by R600 2016-01-26 04:49:24 +00:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600OptimizeVectorRegisters.cpp AMDGPU: Remove implicit ilist iterator conversions, NFC 2015-10-13 20:07:10 +00:00
R600Packetizer.cpp [Packetizer] Add AliasAnalysis as a parameter to the packetizer 2015-12-14 20:35:13 +00:00
R600RegisterInfo.cpp
…
R600RegisterInfo.h AMDGPU: Remove dead code 2015-09-19 06:41:10 +00:00
R600RegisterInfo.td
…
R600Schedule.td
…
R600TextureIntrinsicsReplacer.cpp AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix 2016-01-22 19:00:09 +00:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp AMDGPU: Change control flow intrinsics to use amdgcn prefix 2016-01-22 18:42:55 +00:00
SIDefines.h AMDGPU/SI: Add new target attribute InitialPSInputAddr 2016-01-13 11:45:36 +00:00
SIFixControlFlowLiveIntervals.cpp AMDGPU: Remove unused includes 2015-09-25 00:28:43 +00:00
SIFixSGPRCopies.cpp AMDGPU/SI: Fold operands with sub-registers 2016-01-07 17:10:29 +00:00
SIFixSGPRLiveRanges.cpp AMDGPU: Remove implicit ilist iterator conversions, NFC 2015-10-13 20:07:10 +00:00
SIFoldOperands.cpp AMDGPU: Fix passes depending on dominator tree for no reason 2016-02-11 06:15:34 +00:00
SIFrameLowering.cpp AMDGPU/SI: Do not move scratch resource register on Tonga & Iceland 2016-01-05 20:42:49 +00:00
SIFrameLowering.h AMDGPU: Remove SIPrepareScratchRegs 2015-11-30 21:15:53 +00:00
SIISelLowering.cpp AMDGPU: Split R600 and SI store lowering 2016-02-11 05:32:46 +00:00
SIISelLowering.h AMDGPU: Match some med3 patterns 2016-01-28 20:53:42 +00:00
SIInsertWaits.cpp AMDGPU/SI: Implement a work-around for smrd corrupting vccz bit 2016-02-08 19:49:20 +00:00
SIInstrFormats.td [AMDGPU] Assembler: Fix VOP3 only instructions 2016-02-11 03:28:15 +00:00
SIInstrInfo.cpp AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklist 2016-02-11 21:14:34 +00:00
SIInstrInfo.h AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfo 2016-02-05 18:44:57 +00:00
SIInstrInfo.td [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsing 2016-02-11 18:25:26 +00:00
SIInstructions.td [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsing 2016-02-11 18:25:26 +00:00
SIIntrinsics.td AMDGPU: Remove old sample intrinsics 2016-01-26 04:38:08 +00:00
SILoadStoreOptimizer.cpp AMDGPU/SI: Fix read2 merging into a super register. 2015-07-14 17:57:36 +00:00
SILowerControlFlow.cpp AMDGPU: Fix adding redundant m0 uses 2015-10-21 22:37:51 +00:00
SILowerI1Copies.cpp AMDGPU: Fix passes depending on dominator tree for no reason 2016-02-11 06:15:34 +00:00
SIMachineFunctionInfo.cpp AMDGPU/SI: Add s_waitcnt at the end of non-void functions 2016-01-13 17:23:09 +00:00
SIMachineFunctionInfo.h AMDGPU/SI: Add s_waitcnt at the end of non-void functions 2016-01-13 17:23:09 +00:00
SIMachineScheduler.cpp RegisterPressure: Make liveness tracking subregister aware 2016-01-20 00:23:26 +00:00
SIMachineScheduler.h RegisterPressure: Make liveness tracking subregister aware 2016-01-20 00:23:26 +00:00
SIRegisterInfo.cpp AMDGPU: Release the scavenged offset register during VGPR spill 2016-02-10 20:13:58 +00:00
SIRegisterInfo.h AMDGPU/SI: Add SI Machine Scheduler 2016-01-13 16:10:10 +00:00
SIRegisterInfo.td AMDGPU: Make v32i8/v64i8 illegal types 2016-01-26 04:43:48 +00:00
SISchedule.td AMDGPU: Improve accuracy of instruction rates for VOPC 2015-09-25 16:58:25 +00:00
SIShrinkInstructions.cpp AMDGPU: Add MachineInstr overloads for instruction format tests 2015-10-20 04:35:43 +00:00
SITypeRewriter.cpp AMDGPU/SI: Fix crash when inline assembly is used in a graphics shader 2016-01-06 22:01:04 +00:00
VIInstrFormats.td
…
VIInstructions.td AMDGPU/SI: Move VI SMEM pattern back into VIInstructions.td 2016-01-04 20:23:10 +00:00