forked from OSchip/llvm-project
987 lines
22 KiB
LLVM
987 lines
22 KiB
LLVM
; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
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; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define double @test1(double %a, double %b) {
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entry:
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%v = fmul double %a, %b
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ret double %v
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; CHECK-LABEL: @test1
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; CHECK: xsmuldp 1, 1, 2
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; CHECK: blr
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}
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define double @test2(double %a, double %b) {
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entry:
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%v = fdiv double %a, %b
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ret double %v
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; CHECK-LABEL: @test2
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; CHECK: xsdivdp 1, 1, 2
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; CHECK: blr
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}
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define double @test3(double %a, double %b) {
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entry:
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%v = fadd double %a, %b
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ret double %v
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; CHECK-LABEL: @test3
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; CHECK: xsadddp 1, 1, 2
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; CHECK: blr
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}
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define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
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entry:
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%v = fadd <2 x double> %a, %b
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ret <2 x double> %v
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; CHECK-LABEL: @test4
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; CHECK: xvadddp 34, 34, 35
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; CHECK: blr
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}
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define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%v = xor <4 x i32> %a, %b
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ret <4 x i32> %v
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; CHECK-REG-LABEL: @test5
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; CHECK-REG: xxlxor 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test5
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlxor 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: blr
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}
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define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%v = xor <8 x i16> %a, %b
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ret <8 x i16> %v
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; CHECK-REG-LABEL: @test6
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; CHECK-REG: xxlxor 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test6
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlxor 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: blr
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}
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define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%v = xor <16 x i8> %a, %b
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ret <16 x i8> %v
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; CHECK-REG-LABEL: @test7
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; CHECK-REG: xxlxor 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test7
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlxor 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: blr
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}
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define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%v = or <4 x i32> %a, %b
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ret <4 x i32> %v
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; CHECK-REG-LABEL: @test8
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; CHECK-REG: xxlor 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test8
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlor 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: blr
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}
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define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%v = or <8 x i16> %a, %b
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ret <8 x i16> %v
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; CHECK-REG-LABEL: @test9
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; CHECK-REG: xxlor 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test9
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlor 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: blr
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}
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define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%v = or <16 x i8> %a, %b
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ret <16 x i8> %v
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; CHECK-REG-LABEL: @test10
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; CHECK-REG: xxlor 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test10
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlor 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: blr
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}
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define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%v = and <4 x i32> %a, %b
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ret <4 x i32> %v
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; CHECK-REG-LABEL: @test11
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; CHECK-REG: xxland 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test11
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxland 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: blr
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}
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define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%v = and <8 x i16> %a, %b
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ret <8 x i16> %v
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; CHECK-REG-LABEL: @test12
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; CHECK-REG: xxland 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test12
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxland 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: blr
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}
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define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%v = and <16 x i8> %a, %b
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ret <16 x i8> %v
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; CHECK-REG-LABEL: @test13
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; CHECK-REG: xxland 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test13
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxland 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: blr
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}
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define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%v = or <4 x i32> %a, %b
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%w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %w
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; CHECK-REG-LABEL: @test14
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; CHECK-REG: xxlnor 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test14
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlor 36, 36, 37
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; CHECK-FISL: vor 0, 4, 4
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlnor 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: lis 0, -1
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; CHECK-FISL: ori 0, 0, 65520
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; CHECK-FISL: stvx 0, 1, 0
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; CHECK-FISL: blr
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}
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define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%v = or <8 x i16> %a, %b
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%w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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ret <8 x i16> %w
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; CHECK-REG-LABEL: @test15
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; CHECK-REG: xxlnor 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test15
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlor 36, 36, 37
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; CHECK-FISL: vor 0, 4, 4
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlnor 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: lis 0, -1
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; CHECK-FISL: ori 0, 0, 65520
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; CHECK-FISL: stvx 0, 1, 0
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; CHECK-FISL: blr
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}
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define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%v = or <16 x i8> %a, %b
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%w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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ret <16 x i8> %w
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; CHECK-REG-LABEL: @test16
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; CHECK-REG: xxlnor 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test16
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlor 36, 36, 37
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; CHECK-FISL: vor 0, 4, 4
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; CHECK-FISL: vor 4, 2, 2
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: xxlnor 36, 36, 37
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; CHECK-FISL: vor 2, 4, 4
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; CHECK-FISL: lis 0, -1
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; CHECK-FISL: ori 0, 0, 65520
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; CHECK-FISL: stvx 0, 1, 0
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; CHECK-FISL: blr
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}
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define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
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%v = and <4 x i32> %a, %w
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ret <4 x i32> %v
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; CHECK-REG-LABEL: @test17
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; CHECK-REG: xxlandc 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test17
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; CHECK-FISL: vspltisb 4, -1
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: vor 0, 4, 4
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; CHECK-FISL: xxlxor 37, 37, 32
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; CHECK-FISL: vor 3, 5, 5
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; CHECK-FISL: vor 5, 2, 2
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; CHECK-FISL: vor 0, 3, 3
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; CHECK-FISL: xxland 37, 37, 32
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; CHECK-FISL: vor 2, 5, 5
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; CHECK-FISL: blr
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}
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define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%v = and <8 x i16> %a, %w
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ret <8 x i16> %v
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; CHECK-REG-LABEL: @test18
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; CHECK-REG: xxlandc 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test18
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; CHECK-FISL: vspltisb 4, -1
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: vor 0, 4, 4
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; CHECK-FISL: xxlxor 37, 37, 32
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; CHECK-FISL: vor 4, 5, 5
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; CHECK-FISL: vor 5, 2, 2
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; CHECK-FISL: vor 0, 3, 3
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; CHECK-FISL: xxlandc 37, 37, 32
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; CHECK-FISL: vor 2, 5, 5
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; CHECK-FISL: lis 0, -1
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; CHECK-FISL: ori 0, 0, 65520
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; CHECK-FISL: stvx 4, 1, 0
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; CHECK-FISL: blr
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}
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define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%v = and <16 x i8> %a, %w
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ret <16 x i8> %v
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; CHECK-REG-LABEL: @test19
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; CHECK-REG: xxlandc 34, 34, 35
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test19
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; CHECK-FISL: vspltisb 4, -1
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; CHECK-FISL: vor 5, 3, 3
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; CHECK-FISL: vor 0, 4, 4
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; CHECK-FISL: xxlxor 37, 37, 32
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; CHECK-FISL: vor 4, 5, 5
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; CHECK-FISL: vor 5, 2, 2
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; CHECK-FISL: vor 0, 3, 3
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; CHECK-FISL: xxlandc 37, 37, 32
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; CHECK-FISL: vor 2, 5, 5
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; CHECK-FISL: lis 0, -1
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; CHECK-FISL: ori 0, 0, 65520
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; CHECK-FISL: stvx 4, 1, 0
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; CHECK-FISL: blr
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}
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define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
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entry:
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%m = icmp eq <4 x i32> %c, %d
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%v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %v
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; CHECK-REG-LABEL: @test20
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; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5
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; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test20
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; CHECK-FISL: vcmpequw 4, 4, 5
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; CHECK-FISL: vor 0, 3, 3
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; CHECK-FISL: vor 1, 2, 2
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; CHECK-FISL: vor 6, 4, 4
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; CHECK-FISL: xxsel 32, 32, 33, 38
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; CHECK-FISL: vor 2, 0, 0
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; CHECK-FISL: blr
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}
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define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
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entry:
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%m = fcmp oeq <4 x float> %c, %d
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%v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
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ret <4 x float> %v
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; CHECK-REG-LABEL: @test21
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; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37
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; CHECK-REG: xxsel 34, 35, 34, [[V1]]
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test21
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; CHECK-FISL: vor 0, 5, 5
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; CHECK-FISL: vor 1, 4, 4
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; CHECK-FISL: vor 6, 3, 3
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; CHECK-FISL: vor 7, 2, 2
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; CHECK-FISL: xvcmpeqsp 32, 33, 32
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; CHECK-FISL: xxsel 32, 38, 39, 32
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; CHECK-FISL: vor 2, 0, 0
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; CHECK-FISL: blr
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}
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define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
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entry:
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%m = fcmp ueq <4 x float> %c, %d
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%v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
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ret <4 x float> %v
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; CHECK-REG-LABEL: @test22
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; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
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; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
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; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
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; CHECK-REG-DAG: xxlnor
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; CHECK-REG-DAG: xxlnor
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; CHECK-REG-DAG: xxlor
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; CHECK-REG-DAG: xxlor
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; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test22
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; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 32
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; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 32, 32
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; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 33
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; CHECK-FISL-DAG: xxlnor
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; CHECK-FISL-DAG: xxlnor
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; CHECK-FISL-DAG: xxlor
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; CHECK-FISL-DAG: xxlor
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; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}}
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; CHECK-FISL: blr
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}
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define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
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entry:
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%m = icmp eq <8 x i16> %c, %d
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%v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %v
|
|
|
|
; CHECK-REG-LABEL: @test23
|
|
; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5
|
|
; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test23
|
|
; CHECK-FISL: vcmpequh 4, 4, 5
|
|
; CHECK-FISL: vor 0, 3, 3
|
|
; CHECK-FISL: vor 1, 2, 2
|
|
; CHECK-FISL: vor 6, 4, 4
|
|
; CHECK-FISL: xxsel 32, 32, 33, 38
|
|
; CHECK-FISL: vor 2, 0,
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
|
|
entry:
|
|
%m = icmp eq <16 x i8> %c, %d
|
|
%v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
|
|
ret <16 x i8> %v
|
|
|
|
; CHECK-REG-LABEL: @test24
|
|
; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5
|
|
; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test24
|
|
; CHECK-FISL: vcmpequb 4, 4, 5
|
|
; CHECK-FISL: vor 0, 3, 3
|
|
; CHECK-FISL: vor 1, 2, 2
|
|
; CHECK-FISL: vor 6, 4, 4
|
|
; CHECK-FISL: xxsel 32, 32, 33, 38
|
|
; CHECK-FISL: vor 2, 0, 0
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
|
|
entry:
|
|
%m = fcmp oeq <2 x double> %c, %d
|
|
%v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test25
|
|
; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37
|
|
; CHECK: xxsel 34, 35, 34, [[V1]]
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
|
|
%v = add <2 x i64> %a, %b
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test26
|
|
|
|
; Make sure we use only two stores (one for each operand).
|
|
; CHECK: stxvd2x 35,
|
|
; CHECK: stxvd2x 34,
|
|
; CHECK-NOT: stxvd2x
|
|
|
|
; FIXME: The code quality here is not good; just make sure we do something for now.
|
|
; CHECK: add
|
|
; CHECK: add
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
|
|
%v = and <2 x i64> %a, %b
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test27
|
|
; CHECK: xxland 34, 34, 35
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test28(<2 x double>* %a) {
|
|
%v = load <2 x double>, <2 x double>* %a, align 16
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test28
|
|
; CHECK: lxvd2x 34, 0, 3
|
|
; CHECK: blr
|
|
}
|
|
|
|
define void @test29(<2 x double>* %a, <2 x double> %b) {
|
|
store <2 x double> %b, <2 x double>* %a, align 16
|
|
ret void
|
|
|
|
; CHECK-LABEL: @test29
|
|
; CHECK: stxvd2x 34, 0, 3
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test28u(<2 x double>* %a) {
|
|
%v = load <2 x double>, <2 x double>* %a, align 8
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test28u
|
|
; CHECK: lxvd2x 34, 0, 3
|
|
; CHECK: blr
|
|
}
|
|
|
|
define void @test29u(<2 x double>* %a, <2 x double> %b) {
|
|
store <2 x double> %b, <2 x double>* %a, align 8
|
|
ret void
|
|
|
|
; CHECK-LABEL: @test29u
|
|
; CHECK: stxvd2x 34, 0, 3
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test30(<2 x i64>* %a) {
|
|
%v = load <2 x i64>, <2 x i64>* %a, align 16
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-REG-LABEL: @test30
|
|
; CHECK-REG: lxvd2x 34, 0, 3
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test30
|
|
; CHECK-FISL: lxvd2x 0, 0, 3
|
|
; CHECK-FISL: xxlor 34, 0, 0
|
|
; CHECK-FISL: vor 3, 2, 2
|
|
; CHECK-FISL: vor 2, 3, 3
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define void @test31(<2 x i64>* %a, <2 x i64> %b) {
|
|
store <2 x i64> %b, <2 x i64>* %a, align 16
|
|
ret void
|
|
|
|
; CHECK-LABEL: @test31
|
|
; CHECK: stxvd2x 34, 0, 3
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <4 x float> @test32(<4 x float>* %a) {
|
|
%v = load <4 x float>, <4 x float>* %a, align 16
|
|
ret <4 x float> %v
|
|
|
|
; CHECK-REG-LABEL: @test32
|
|
; CHECK-REG: lxvw4x 34, 0, 3
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test32
|
|
; CHECK-FISL: lxvw4x 0, 0, 3
|
|
; CHECK-FISL: xxlor 34, 0, 0
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define void @test33(<4 x float>* %a, <4 x float> %b) {
|
|
store <4 x float> %b, <4 x float>* %a, align 16
|
|
ret void
|
|
|
|
; CHECK-REG-LABEL: @test33
|
|
; CHECK-REG: stxvw4x 34, 0, 3
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test33
|
|
; CHECK-FISL: vor 3, 2, 2
|
|
; CHECK-FISL: stxvw4x 35, 0, 3
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define <4 x float> @test32u(<4 x float>* %a) {
|
|
%v = load <4 x float>, <4 x float>* %a, align 8
|
|
ret <4 x float> %v
|
|
|
|
; CHECK-LABEL: @test32u
|
|
; CHECK-DAG: lvsl
|
|
; CHECK-DAG: lvx
|
|
; CHECK-DAG: lvx
|
|
; CHECK: vperm 2,
|
|
; CHECK: blr
|
|
}
|
|
|
|
define void @test33u(<4 x float>* %a, <4 x float> %b) {
|
|
store <4 x float> %b, <4 x float>* %a, align 8
|
|
ret void
|
|
|
|
; CHECK-REG-LABEL: @test33u
|
|
; CHECK-REG: stxvw4x 34, 0, 3
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test33u
|
|
; CHECK-FISL: vor 3, 2, 2
|
|
; CHECK-FISL: stxvw4x 35, 0, 3
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define <4 x i32> @test34(<4 x i32>* %a) {
|
|
%v = load <4 x i32>, <4 x i32>* %a, align 16
|
|
ret <4 x i32> %v
|
|
|
|
; CHECK-REG-LABEL: @test34
|
|
; CHECK-REG: lxvw4x 34, 0, 3
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test34
|
|
; CHECK-FISL: lxvw4x 0, 0, 3
|
|
; CHECK-FISL: xxlor 34, 0, 0
|
|
; CHECK-FISL: vor 3, 2, 2
|
|
; CHECK-FISL: vor 2, 3, 3
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define void @test35(<4 x i32>* %a, <4 x i32> %b) {
|
|
store <4 x i32> %b, <4 x i32>* %a, align 16
|
|
ret void
|
|
|
|
; CHECK-REG-LABEL: @test35
|
|
; CHECK-REG: stxvw4x 34, 0, 3
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test35
|
|
; CHECK-FISL: vor 3, 2, 2
|
|
; CHECK-FISL: stxvw4x 35, 0, 3
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define <2 x double> @test40(<2 x i64> %a) {
|
|
%v = uitofp <2 x i64> %a to <2 x double>
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test40
|
|
; CHECK: xvcvuxddp 34, 34
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test41(<2 x i64> %a) {
|
|
%v = sitofp <2 x i64> %a to <2 x double>
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test41
|
|
; CHECK: xvcvsxddp 34, 34
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test42(<2 x double> %a) {
|
|
%v = fptoui <2 x double> %a to <2 x i64>
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test42
|
|
; CHECK: xvcvdpuxds 34, 34
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test43(<2 x double> %a) {
|
|
%v = fptosi <2 x double> %a to <2 x i64>
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test43
|
|
; CHECK: xvcvdpsxds 34, 34
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x float> @test44(<2 x i64> %a) {
|
|
%v = uitofp <2 x i64> %a to <2 x float>
|
|
ret <2 x float> %v
|
|
|
|
; CHECK-LABEL: @test44
|
|
; FIXME: The code quality here looks pretty bad.
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x float> @test45(<2 x i64> %a) {
|
|
%v = sitofp <2 x i64> %a to <2 x float>
|
|
ret <2 x float> %v
|
|
|
|
; CHECK-LABEL: @test45
|
|
; FIXME: The code quality here looks pretty bad.
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test46(<2 x float> %a) {
|
|
%v = fptoui <2 x float> %a to <2 x i64>
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test46
|
|
; FIXME: The code quality here looks pretty bad.
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test47(<2 x float> %a) {
|
|
%v = fptosi <2 x float> %a to <2 x i64>
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test47
|
|
; FIXME: The code quality here looks pretty bad.
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test50(double* %a) {
|
|
%v = load double, double* %a, align 8
|
|
%w = insertelement <2 x double> undef, double %v, i32 0
|
|
%x = insertelement <2 x double> %w, double %v, i32 1
|
|
ret <2 x double> %x
|
|
|
|
; CHECK-LABEL: @test50
|
|
; CHECK: lxvdsx 34, 0, 3
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
|
|
%v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test51
|
|
; CHECK: xxpermdi 34, 34, 34, 0
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
|
|
%v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test52
|
|
; CHECK: xxpermdi 34, 34, 35, 0
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
|
|
%v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test53
|
|
; CHECK: xxpermdi 34, 35, 34, 0
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
|
|
%v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test54
|
|
; CHECK: xxpermdi 34, 34, 35, 2
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
|
|
%v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
|
|
ret <2 x double> %v
|
|
|
|
; CHECK-LABEL: @test55
|
|
; CHECK: xxpermdi 34, 34, 35, 3
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
|
|
%v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test56
|
|
; CHECK: xxpermdi 34, 34, 35, 3
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
|
|
%v = shl <2 x i64> %a, %b
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test60
|
|
; This should scalarize, and the current code quality is not good.
|
|
; CHECK: stxvd2x
|
|
; CHECK: stxvd2x
|
|
; CHECK: sld
|
|
; CHECK: sld
|
|
; CHECK: lxvd2x
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
|
|
%v = lshr <2 x i64> %a, %b
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test61
|
|
; This should scalarize, and the current code quality is not good.
|
|
; CHECK: stxvd2x
|
|
; CHECK: stxvd2x
|
|
; CHECK: srd
|
|
; CHECK: srd
|
|
; CHECK: lxvd2x
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
|
|
%v = ashr <2 x i64> %a, %b
|
|
ret <2 x i64> %v
|
|
|
|
; CHECK-LABEL: @test62
|
|
; This should scalarize, and the current code quality is not good.
|
|
; CHECK: stxvd2x
|
|
; CHECK: stxvd2x
|
|
; CHECK: srad
|
|
; CHECK: srad
|
|
; CHECK: lxvd2x
|
|
; CHECK: blr
|
|
}
|
|
|
|
define double @test63(<2 x double> %a) {
|
|
%v = extractelement <2 x double> %a, i32 0
|
|
ret double %v
|
|
|
|
; CHECK-REG-LABEL: @test63
|
|
; CHECK-REG: xxlor 1, 34, 34
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test63
|
|
; CHECK-FISL: xxlor 0, 34, 34
|
|
; CHECK-FISL: fmr 1, 0
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define double @test64(<2 x double> %a) {
|
|
%v = extractelement <2 x double> %a, i32 1
|
|
ret double %v
|
|
|
|
; CHECK-REG-LABEL: @test64
|
|
; CHECK-REG: xxpermdi 1, 34, 34, 2
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test64
|
|
; CHECK-FISL: xxpermdi 34, 34, 34, 2
|
|
; CHECK-FISL: xxlor 0, 34, 34
|
|
; CHECK-FISL: fmr 1, 0
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
|
|
%w = icmp eq <2 x i64> %a, %b
|
|
ret <2 x i1> %w
|
|
|
|
; CHECK-REG-LABEL: @test65
|
|
; CHECK-REG: vcmpequw 2, 2, 3
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test65
|
|
; CHECK-FISL: vor 4, 3, 3
|
|
; CHECK-FISL: vor 5, 2, 2
|
|
; CHECK-FISL: vcmpequw 4, 5, 4
|
|
; CHECK-FISL: vor 2, 4, 4
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
|
|
%w = icmp ne <2 x i64> %a, %b
|
|
ret <2 x i1> %w
|
|
|
|
; CHECK-REG-LABEL: @test66
|
|
; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3
|
|
; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test66
|
|
; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4
|
|
; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
|
|
%w = icmp ult <2 x i64> %a, %b
|
|
ret <2 x i1> %w
|
|
|
|
; CHECK-LABEL: @test67
|
|
; This should scalarize, and the current code quality is not good.
|
|
; CHECK: stxvd2x
|
|
; CHECK: stxvd2x
|
|
; CHECK: cmpld
|
|
; CHECK: cmpld
|
|
; CHECK: lxvd2x
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test68(<2 x i32> %a) {
|
|
%w = sitofp <2 x i32> %a to <2 x double>
|
|
ret <2 x double> %w
|
|
|
|
; CHECK-LABEL: @test68
|
|
; CHECK: xxsldwi [[V1:[0-9]+]], 34, 34, 1
|
|
; CHECK: xvcvsxwdp 34, [[V1]]
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test69(<2 x i16> %a) {
|
|
%w = sitofp <2 x i16> %a to <2 x double>
|
|
ret <2 x double> %w
|
|
|
|
; CHECK-LABEL: @test69
|
|
; CHECK: vspltisw [[V1:[0-9]+]], 8
|
|
; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
|
|
; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
|
|
; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
|
|
; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
|
|
; CHECK: xvcvsxwdp 34, [[V4]]
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x double> @test70(<2 x i8> %a) {
|
|
%w = sitofp <2 x i8> %a to <2 x double>
|
|
ret <2 x double> %w
|
|
|
|
; CHECK-LABEL: @test70
|
|
; CHECK: vspltisw [[V1:[0-9]+]], 12
|
|
; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
|
|
; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
|
|
; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
|
|
; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
|
|
; CHECK: xvcvsxwdp 34, [[V4]]
|
|
; CHECK: blr
|
|
}
|
|
|
|
define <2 x i32> @test80(i32 %v) {
|
|
%b1 = insertelement <2 x i32> undef, i32 %v, i32 0
|
|
%b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
|
|
%i = add <2 x i32> %b2, <i32 2, i32 3>
|
|
ret <2 x i32> %i
|
|
|
|
; CHECK-REG-LABEL: @test80
|
|
; CHECK-REG-DAG: addi [[R1:[0-9]+]], 3, 3
|
|
; CHECK-REG-DAG: addi [[R2:[0-9]+]], 1, -16
|
|
; CHECK-REG-DAG: addi [[R3:[0-9]+]], 3, 2
|
|
; CHECK-REG: std [[R1]], -8(1)
|
|
; CHECK-REG: std [[R3]], -16(1)
|
|
; CHECK-REG: lxvd2x 34, 0, [[R2]]
|
|
; CHECK-REG-NOT: stxvd2x
|
|
; CHECK-REG: blr
|
|
|
|
; CHECK-FISL-LABEL: @test80
|
|
; CHECK-FISL-DAG: addi [[R1:[0-9]+]], 3, 3
|
|
; CHECK-FISL-DAG: addi [[R2:[0-9]+]], 1, -16
|
|
; CHECK-FISL-DAG: addi [[R3:[0-9]+]], 3, 2
|
|
; CHECK-FISL-DAG: std [[R1]], -8(1)
|
|
; CHECK-FISL-DAG: std [[R3]], -16(1)
|
|
; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]]
|
|
; CHECK-FISL: blr
|
|
}
|
|
|
|
define <2 x double> @test81(<4 x float> %b) {
|
|
%w = bitcast <4 x float> %b to <2 x double>
|
|
ret <2 x double> %w
|
|
|
|
; CHECK-LABEL: @test81
|
|
; CHECK: blr
|
|
}
|
|
|
|
define double @test82(double %a, double %b, double %c, double %d) {
|
|
entry:
|
|
%m = fcmp oeq double %c, %d
|
|
%v = select i1 %m, double %a, double %b
|
|
ret double %v
|
|
|
|
; CHECK-REG-LABEL: @test82
|
|
; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4
|
|
; CHECK-REG: beqlr [[REG]]
|
|
|
|
; CHECK-FISL-LABEL: @test82
|
|
; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4
|
|
; CHECK-FISL: beq [[REG]], {{.*}}
|
|
}
|