forked from OSchip/llvm-project
455 lines
22 KiB
TableGen
455 lines
22 KiB
TableGen
//====- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 MMX instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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// All instructions that use MMX should be in this file, even if they also use
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// SSE.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MMX Multiclasses
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//===----------------------------------------------------------------------===//
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let Constraints = "$src1 = $dst" in {
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// MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
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// When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
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multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
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bit Commutable = 0> {
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def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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}
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def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (load_mmx addr:$src2))))]>;
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}
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multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
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string OpcodeStr, Intrinsic IntId,
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Intrinsic IntId2> {
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def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
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def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (load_mmx addr:$src2))))]>;
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def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
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(ins VR64:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
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}
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}
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/// Unary MMX instructions requiring SSSE3.
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multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst, (IntId64 VR64:$src))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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(IntId64 (bitconvert (memopmmx addr:$src))))]>;
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}
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/// Binary MMX instructions requiring SSSE3.
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let ImmT = NoImm, Constraints = "$src1 = $dst" in {
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multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64> {
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let isCommutable = 0 in
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopmmx addr:$src2))))]>;
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}
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}
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/// PALIGN MMX instructions (require SSSE3).
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multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
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def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>;
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def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>;
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}
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multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
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string asm, Domain d> {
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def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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[(set DstRC:$dst, (Int SrcRC:$src))], d>;
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def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
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[(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
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}
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multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
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RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
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PatFrag ld_frag, string asm, Domain d> {
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def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
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asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
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def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
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(ins DstRC:$src1, x86memop:$src2), asm,
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[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
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}
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//===----------------------------------------------------------------------===//
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// MMX EMMS Instruction
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//===----------------------------------------------------------------------===//
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def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
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[(int_x86_mmx_emms)]>;
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//===----------------------------------------------------------------------===//
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// MMX Scalar Instructions
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//===----------------------------------------------------------------------===//
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// Data Transfer Instructions
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def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(x86mmx (scalar_to_vector GR32:$src)))]>;
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let canFoldAsLoad = 1 in
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def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(x86mmx (scalar_to_vector (loadi32 addr:$src))))]>;
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let mayStore = 1 in
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def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
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"movd\t{$src, $dst|$dst, $src}", []>;
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def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
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"movd\t{$src, $dst|$dst, $src}", []>;
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let neverHasSideEffects = 1 in
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def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[]>;
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// These are 64 bit moves, but since the OS X assembler doesn't
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// recognize a register-register movq, we write them as
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// movd.
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def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
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(outs GR64:$dst), (ins VR64:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst,
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(bitconvert VR64:$src))]>;
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def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(bitconvert GR64:$src))]>;
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let neverHasSideEffects = 1 in
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def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
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"movq\t{$src, $dst|$dst, $src}", []>;
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let canFoldAsLoad = 1 in
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def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (load_mmx addr:$src))]>;
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def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(store (x86mmx VR64:$src), addr:$dst)]>;
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def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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"movdq2q\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(x86mmx (bitconvert
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(i64 (vector_extract (v2i64 VR128:$src),
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(iPTR 0))))))]>;
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def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
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"movq2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(v2i64 (scalar_to_vector
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(i64 (bitconvert (x86mmx VR64:$src))))))]>;
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let neverHasSideEffects = 1 in
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def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src),
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"movq2dq\t{$src, $dst|$dst, $src}", []>;
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def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src),
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"movdq2q\t{$src, $dst|$dst, $src}", []>;
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def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
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"movntq\t{$src, $dst|$dst, $src}",
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[(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
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let AddedComplexity = 15 in
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// movd to MMX register zero-extends
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def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))))]>;
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let AddedComplexity = 20 in
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def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
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(ins i32mem:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(x86mmx (X86vzmovl (x86mmx
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(scalar_to_vector (loadi32 addr:$src))))))]>;
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// Arithmetic Instructions
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defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b>;
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defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w>;
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defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d>;
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// -- Addition
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defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 1>;
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defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 1>;
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defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 1>;
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defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 1>;
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defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
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defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
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defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
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defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
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defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w>;
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defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d>;
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defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw>;
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// -- Subtraction
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defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b>;
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defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w>;
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defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d>;
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defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q>;
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defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
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defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
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defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
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defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
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defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w>;
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defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d>;
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defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw>;
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// -- Multiplication
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defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>;
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defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
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defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
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defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
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let isCommutable = 1 in
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defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
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int_x86_ssse3_pmul_hr_sw>;
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// -- Miscellanea
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defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
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defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
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int_x86_ssse3_pmadd_ub_sw>;
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defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
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defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
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defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
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defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
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defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
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defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
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defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
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defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b>;
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defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w>;
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defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d>;
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let Constraints = "$src1 = $dst" in
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defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
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// Logical Instructions
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defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 1>;
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defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 1>;
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defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 1>;
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defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn>;
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// Shift Instructions
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defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
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int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
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defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
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int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
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defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
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int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
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defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
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int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
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defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
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int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
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defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
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int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
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defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
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int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
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defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
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int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
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// Comparison Instructions
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defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
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defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
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defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
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defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
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defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
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defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
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// -- Unpack Instructions
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defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
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int_x86_mmx_punpckhbw>;
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defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
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int_x86_mmx_punpckhwd>;
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defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
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int_x86_mmx_punpckhdq>;
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defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
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int_x86_mmx_punpcklbw>;
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defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
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int_x86_mmx_punpcklwd>;
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defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
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int_x86_mmx_punpckldq>;
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// -- Pack Instructions
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defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
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defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
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defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
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// -- Shuffle Instructions
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defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b>;
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def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
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"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR64:$dst,
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(int_x86_sse_pshuf_w VR64:$src1, imm:$src2))]>;
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def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
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(outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
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"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR64:$dst,
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(int_x86_sse_pshuf_w (load_mmx addr:$src1),
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imm:$src2))]>;
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// -- Conversion Instructions
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defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
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f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
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f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
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f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
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f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
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i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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let Constraints = "$src1 = $dst" in {
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defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
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int_x86_sse_cvtpi2ps,
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i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
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SSEPackedSingle>, TB;
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}
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// Extract / Insert
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def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,
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(outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2),
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"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1,
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(iPTR imm:$src2)))]>;
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let Constraints = "$src1 = $dst" in {
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def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,
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(outs VR64:$dst),
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(ins VR64:$src1, GR32:$src2, i32i8imm:$src3),
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"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
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GR32:$src2, (iPTR imm:$src3)))]>;
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def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,
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(outs VR64:$dst),
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(ins VR64:$src1, i16mem:$src2, i32i8imm:$src3),
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"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
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(i32 (anyext (loadi16 addr:$src2))),
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(iPTR imm:$src3)))]>;
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}
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// Mask creation
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def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
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"pmovmskb\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst,
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(int_x86_mmx_pmovmskb VR64:$src))]>;
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// MMX to XMM for vector types
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def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
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[SDTCisVT<0, v2i64>, SDTCisVT<1, x86mmx>]>>;
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def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
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(v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
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def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
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(v2i64 (MOVQI2PQIrm addr:$src))>;
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def : Pat<(v2i64 (MMX_X86movq2dq
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(x86mmx (scalar_to_vector (loadi32 addr:$src))))),
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(v2i64 (MOVDI2PDIrm addr:$src))>;
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// Low word of XMM to MMX.
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def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
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[SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
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def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
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(x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
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def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))),
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(x86mmx (MMX_MOVQ64rm addr:$src))>;
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// Misc.
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|
let Uses = [EDI] in
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def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
|
|
"maskmovq\t{$mask, $src|$src, $mask}",
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[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
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|
let Uses = [RDI] in
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def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
|
|
"maskmovq\t{$mask, $src|$src, $mask}",
|
|
[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
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|
// 64-bit bit convert.
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|
def : Pat<(x86mmx (bitconvert (i64 GR64:$src))),
|
|
(MMX_MOVD64to64rr GR64:$src)>;
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|
def : Pat<(i64 (bitconvert (x86mmx VR64:$src))),
|
|
(MMX_MOVD64from64rr VR64:$src)>;
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|
def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
|
|
(MMX_MOVQ2FR64rr VR64:$src)>;
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|
def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
|
|
(MMX_MOVFR642Qrr FR64:$src)>;
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