forked from OSchip/llvm-project
1294 lines
44 KiB
C++
1294 lines
44 KiB
C++
//===- X86InstructionSelector.cpp -----------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the InstructionSelector class for
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/// X86.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86InstrBuilder.h"
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#include "X86InstrInfo.h"
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#include "X86RegisterBankInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/Support/AtomicOrdering.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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#include <tuple>
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#define DEBUG_TYPE "X86-isel"
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using namespace llvm;
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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class X86InstructionSelector : public InstructionSelector {
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public:
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X86InstructionSelector(const X86TargetMachine &TM, const X86Subtarget &STI,
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const X86RegisterBankInfo &RBI);
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bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
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static const char *getName() { return DEBUG_TYPE; }
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private:
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/// tblgen-erated 'select' implementation, used as the initial selector for
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/// the patterns that don't require complex C++.
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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// TODO: remove after supported by Tablegen-erated instruction selection.
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unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
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uint64_t Alignment) const;
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bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectTrunc(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF,
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CodeGenCoverage &CoverageInfo) const;
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bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF,
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CodeGenCoverage &CoverageInfo) const;
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bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool materializeFP(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
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// emit insert subreg instruction and insert it before MachineInstr &I
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bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
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MachineRegisterInfo &MRI, MachineFunction &MF) const;
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// emit extract subreg instruction and insert it before MachineInstr &I
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bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
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MachineRegisterInfo &MRI, MachineFunction &MF) const;
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const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
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const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
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MachineRegisterInfo &MRI) const;
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const X86TargetMachine &TM;
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const X86Subtarget &STI;
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const X86InstrInfo &TII;
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const X86RegisterInfo &TRI;
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const X86RegisterBankInfo &RBI;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // end anonymous namespace
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#define GET_GLOBALISEL_IMPL
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_IMPL
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X86InstructionSelector::X86InstructionSelector(const X86TargetMachine &TM,
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const X86Subtarget &STI,
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const X86RegisterBankInfo &RBI)
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: InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
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TRI(*STI.getRegisterInfo()), RBI(RBI),
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#define GET_GLOBALISEL_PREDICATES_INIT
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_INIT
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#define GET_GLOBALISEL_TEMPORARIES_INIT
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_INIT
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{
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}
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// FIXME: This should be target-independent, inferred from the types declared
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// for each class in the bank.
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const TargetRegisterClass *
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X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
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if (RB.getID() == X86::GPRRegBankID) {
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if (Ty.getSizeInBits() <= 8)
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return &X86::GR8RegClass;
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if (Ty.getSizeInBits() == 16)
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return &X86::GR16RegClass;
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if (Ty.getSizeInBits() == 32)
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return &X86::GR32RegClass;
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if (Ty.getSizeInBits() == 64)
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return &X86::GR64RegClass;
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}
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if (RB.getID() == X86::VECRRegBankID) {
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if (Ty.getSizeInBits() == 32)
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return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
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if (Ty.getSizeInBits() == 64)
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return STI.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
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if (Ty.getSizeInBits() == 128)
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return STI.hasAVX512() ? &X86::VR128XRegClass : &X86::VR128RegClass;
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if (Ty.getSizeInBits() == 256)
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return STI.hasAVX512() ? &X86::VR256XRegClass : &X86::VR256RegClass;
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if (Ty.getSizeInBits() == 512)
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return &X86::VR512RegClass;
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}
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llvm_unreachable("Unknown RegBank!");
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}
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const TargetRegisterClass *
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X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg,
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MachineRegisterInfo &MRI) const {
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const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
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return getRegClass(Ty, RegBank);
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}
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static unsigned getSubRegIndex(const TargetRegisterClass *RC) {
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unsigned SubIdx = X86::NoSubRegister;
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if (RC == &X86::GR32RegClass) {
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SubIdx = X86::sub_32bit;
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} else if (RC == &X86::GR16RegClass) {
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SubIdx = X86::sub_16bit;
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} else if (RC == &X86::GR8RegClass) {
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SubIdx = X86::sub_8bit;
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}
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return SubIdx;
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}
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static const TargetRegisterClass *getRegClassFromGRPhysReg(unsigned Reg) {
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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if (X86::GR64RegClass.contains(Reg))
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return &X86::GR64RegClass;
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if (X86::GR32RegClass.contains(Reg))
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return &X86::GR32RegClass;
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if (X86::GR16RegClass.contains(Reg))
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return &X86::GR16RegClass;
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if (X86::GR8RegClass.contains(Reg))
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return &X86::GR8RegClass;
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llvm_unreachable("Unknown RegClass for PhysReg!");
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}
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// Set X86 Opcode and constrain DestReg.
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bool X86InstructionSelector::selectCopy(MachineInstr &I,
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MachineRegisterInfo &MRI) const {
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unsigned DstReg = I.getOperand(0).getReg();
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const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
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const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
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unsigned SrcReg = I.getOperand(1).getReg();
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const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
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const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
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if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
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assert(I.isCopy() && "Generic operators do not allow physical registers");
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if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID &&
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DstRegBank.getID() == X86::GPRRegBankID) {
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const TargetRegisterClass *SrcRC =
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getRegClass(MRI.getType(SrcReg), SrcRegBank);
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const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg);
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if (SrcRC != DstRC) {
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// This case can be generated by ABI lowering, performe anyext
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unsigned ExtSrc = MRI.createVirtualRegister(DstRC);
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BuildMI(*I.getParent(), I, I.getDebugLoc(),
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TII.get(TargetOpcode::SUBREG_TO_REG))
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.addDef(ExtSrc)
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.addImm(0)
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.addReg(SrcReg)
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.addImm(getSubRegIndex(SrcRC));
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I.getOperand(1).setReg(ExtSrc);
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}
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}
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return true;
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}
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assert((!TargetRegisterInfo::isPhysicalRegister(SrcReg) || I.isCopy()) &&
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"No phys reg on generic operators");
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assert((DstSize == SrcSize ||
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// Copies are a mean to setup initial types, the number of
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// bits may not exactly match.
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(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
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"Copy with different width?!");
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const TargetRegisterClass *DstRC =
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getRegClass(MRI.getType(DstReg), DstRegBank);
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if (SrcRegBank.getID() == X86::GPRRegBankID &&
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DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize &&
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TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
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// Change the physical register to performe truncate.
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const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg);
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if (DstRC != SrcRC) {
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I.getOperand(1).setSubReg(getSubRegIndex(DstRC));
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I.getOperand(1).substPhysReg(SrcReg, TRI);
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}
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}
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// No need to constrain SrcReg. It will get constrained when
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// we hit another of its use or its defs.
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// Copies do not have constraints.
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const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
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if (!OldRC || !DstRC->hasSubClassEq(OldRC)) {
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if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
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DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
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<< " operand\n");
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return false;
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}
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}
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I.setDesc(TII.get(X86::COPY));
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return true;
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}
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bool X86InstructionSelector::select(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const {
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assert(I.getParent() && "Instruction should be in a basic block!");
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assert(I.getParent()->getParent() && "Instruction should be in a function!");
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned Opcode = I.getOpcode();
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if (!isPreISelGenericOpcode(Opcode)) {
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// Certain non-generic instructions also need some special handling.
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if (Opcode == TargetOpcode::LOAD_STACK_GUARD)
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return false;
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if (I.isCopy())
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return selectCopy(I, MRI);
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return true;
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}
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assert(I.getNumOperands() == I.getNumExplicitOperands() &&
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"Generic instruction has unexpected implicit operands\n");
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if (selectImpl(I, CoverageInfo))
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return true;
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DEBUG(dbgs() << " C++ instruction selection: "; I.print(dbgs()));
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// TODO: This should be implemented by tblgen.
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switch (I.getOpcode()) {
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default:
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return false;
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case TargetOpcode::G_STORE:
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case TargetOpcode::G_LOAD:
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return selectLoadStoreOp(I, MRI, MF);
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case TargetOpcode::G_GEP:
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case TargetOpcode::G_FRAME_INDEX:
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return selectFrameIndexOrGep(I, MRI, MF);
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case TargetOpcode::G_GLOBAL_VALUE:
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return selectGlobalValue(I, MRI, MF);
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case TargetOpcode::G_CONSTANT:
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return selectConstant(I, MRI, MF);
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case TargetOpcode::G_FCONSTANT:
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return materializeFP(I, MRI, MF);
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case TargetOpcode::G_TRUNC:
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return selectTrunc(I, MRI, MF);
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case TargetOpcode::G_ZEXT:
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return selectZext(I, MRI, MF);
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case TargetOpcode::G_ANYEXT:
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return selectAnyext(I, MRI, MF);
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case TargetOpcode::G_ICMP:
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return selectCmp(I, MRI, MF);
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case TargetOpcode::G_UADDE:
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return selectUadde(I, MRI, MF);
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case TargetOpcode::G_UNMERGE_VALUES:
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return selectUnmergeValues(I, MRI, MF, CoverageInfo);
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case TargetOpcode::G_MERGE_VALUES:
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return selectMergeValues(I, MRI, MF, CoverageInfo);
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case TargetOpcode::G_EXTRACT:
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return selectExtract(I, MRI, MF);
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case TargetOpcode::G_INSERT:
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return selectInsert(I, MRI, MF);
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case TargetOpcode::G_BRCOND:
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return selectCondBranch(I, MRI, MF);
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case TargetOpcode::G_IMPLICIT_DEF:
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case TargetOpcode::G_PHI:
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return selectImplicitDefOrPHI(I, MRI);
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}
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return false;
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}
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unsigned X86InstructionSelector::getLoadStoreOp(const LLT &Ty,
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const RegisterBank &RB,
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unsigned Opc,
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uint64_t Alignment) const {
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bool Isload = (Opc == TargetOpcode::G_LOAD);
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bool HasAVX = STI.hasAVX();
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bool HasAVX512 = STI.hasAVX512();
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bool HasVLX = STI.hasVLX();
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if (Ty == LLT::scalar(8)) {
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if (X86::GPRRegBankID == RB.getID())
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return Isload ? X86::MOV8rm : X86::MOV8mr;
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} else if (Ty == LLT::scalar(16)) {
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if (X86::GPRRegBankID == RB.getID())
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return Isload ? X86::MOV16rm : X86::MOV16mr;
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} else if (Ty == LLT::scalar(32) || Ty == LLT::pointer(0, 32)) {
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if (X86::GPRRegBankID == RB.getID())
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return Isload ? X86::MOV32rm : X86::MOV32mr;
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if (X86::VECRRegBankID == RB.getID())
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return Isload ? (HasAVX512 ? X86::VMOVSSZrm
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: HasAVX ? X86::VMOVSSrm : X86::MOVSSrm)
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: (HasAVX512 ? X86::VMOVSSZmr
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: HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
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} else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
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if (X86::GPRRegBankID == RB.getID())
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return Isload ? X86::MOV64rm : X86::MOV64mr;
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if (X86::VECRRegBankID == RB.getID())
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return Isload ? (HasAVX512 ? X86::VMOVSDZrm
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: HasAVX ? X86::VMOVSDrm : X86::MOVSDrm)
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: (HasAVX512 ? X86::VMOVSDZmr
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: HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
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} else if (Ty.isVector() && Ty.getSizeInBits() == 128) {
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if (Alignment >= 16)
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return Isload ? (HasVLX ? X86::VMOVAPSZ128rm
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: HasAVX512
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? X86::VMOVAPSZ128rm_NOVLX
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: HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
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: (HasVLX ? X86::VMOVAPSZ128mr
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: HasAVX512
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? X86::VMOVAPSZ128mr_NOVLX
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: HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
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else
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return Isload ? (HasVLX ? X86::VMOVUPSZ128rm
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: HasAVX512
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? X86::VMOVUPSZ128rm_NOVLX
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: HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
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: (HasVLX ? X86::VMOVUPSZ128mr
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: HasAVX512
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? X86::VMOVUPSZ128mr_NOVLX
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: HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
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} else if (Ty.isVector() && Ty.getSizeInBits() == 256) {
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if (Alignment >= 32)
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return Isload ? (HasVLX ? X86::VMOVAPSZ256rm
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: HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX
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: X86::VMOVAPSYrm)
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: (HasVLX ? X86::VMOVAPSZ256mr
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: HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX
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: X86::VMOVAPSYmr);
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else
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return Isload ? (HasVLX ? X86::VMOVUPSZ256rm
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: HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX
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: X86::VMOVUPSYrm)
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: (HasVLX ? X86::VMOVUPSZ256mr
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: HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX
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|
: X86::VMOVUPSYmr);
|
|
} else if (Ty.isVector() && Ty.getSizeInBits() == 512) {
|
|
if (Alignment >= 64)
|
|
return Isload ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
|
|
else
|
|
return Isload ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
|
|
}
|
|
return Opc;
|
|
}
|
|
|
|
// Fill in an address from the given instruction.
|
|
static void X86SelectAddress(const MachineInstr &I,
|
|
const MachineRegisterInfo &MRI,
|
|
X86AddressMode &AM) {
|
|
assert(I.getOperand(0).isReg() && "unsupported opperand.");
|
|
assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
|
|
"unsupported type.");
|
|
|
|
if (I.getOpcode() == TargetOpcode::G_GEP) {
|
|
if (auto COff = getConstantVRegVal(I.getOperand(2).getReg(), MRI)) {
|
|
int64_t Imm = *COff;
|
|
if (isInt<32>(Imm)) { // Check for displacement overflow.
|
|
AM.Disp = static_cast<int32_t>(Imm);
|
|
AM.Base.Reg = I.getOperand(1).getReg();
|
|
return;
|
|
}
|
|
}
|
|
} else if (I.getOpcode() == TargetOpcode::G_FRAME_INDEX) {
|
|
AM.Base.FrameIndex = I.getOperand(1).getIndex();
|
|
AM.BaseType = X86AddressMode::FrameIndexBase;
|
|
return;
|
|
}
|
|
|
|
// Default behavior.
|
|
AM.Base.Reg = I.getOperand(0).getReg();
|
|
}
|
|
|
|
bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
unsigned Opc = I.getOpcode();
|
|
|
|
assert((Opc == TargetOpcode::G_STORE || Opc == TargetOpcode::G_LOAD) &&
|
|
"unexpected instruction");
|
|
|
|
const unsigned DefReg = I.getOperand(0).getReg();
|
|
LLT Ty = MRI.getType(DefReg);
|
|
const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
|
|
|
|
auto &MemOp = **I.memoperands_begin();
|
|
if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
|
|
DEBUG(dbgs() << "Atomic load/store not supported yet\n");
|
|
return false;
|
|
}
|
|
|
|
unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlignment());
|
|
if (NewOpc == Opc)
|
|
return false;
|
|
|
|
X86AddressMode AM;
|
|
X86SelectAddress(*MRI.getVRegDef(I.getOperand(1).getReg()), MRI, AM);
|
|
|
|
I.setDesc(TII.get(NewOpc));
|
|
MachineInstrBuilder MIB(MF, I);
|
|
if (Opc == TargetOpcode::G_LOAD) {
|
|
I.RemoveOperand(1);
|
|
addFullAddress(MIB, AM);
|
|
} else {
|
|
// G_STORE (VAL, Addr), X86Store instruction (Addr, VAL)
|
|
I.RemoveOperand(1);
|
|
I.RemoveOperand(0);
|
|
addFullAddress(MIB, AM).addUse(DefReg);
|
|
}
|
|
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
|
|
}
|
|
|
|
static unsigned getLeaOP(LLT Ty, const X86Subtarget &STI) {
|
|
if (Ty == LLT::pointer(0, 64))
|
|
return X86::LEA64r;
|
|
else if (Ty == LLT::pointer(0, 32))
|
|
return STI.isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r;
|
|
else
|
|
llvm_unreachable("Can't get LEA opcode. Unsupported type.");
|
|
}
|
|
|
|
bool X86InstructionSelector::selectFrameIndexOrGep(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
unsigned Opc = I.getOpcode();
|
|
|
|
assert((Opc == TargetOpcode::G_FRAME_INDEX || Opc == TargetOpcode::G_GEP) &&
|
|
"unexpected instruction");
|
|
|
|
const unsigned DefReg = I.getOperand(0).getReg();
|
|
LLT Ty = MRI.getType(DefReg);
|
|
|
|
// Use LEA to calculate frame index and GEP
|
|
unsigned NewOpc = getLeaOP(Ty, STI);
|
|
I.setDesc(TII.get(NewOpc));
|
|
MachineInstrBuilder MIB(MF, I);
|
|
|
|
if (Opc == TargetOpcode::G_FRAME_INDEX) {
|
|
addOffset(MIB, 0);
|
|
} else {
|
|
MachineOperand &InxOp = I.getOperand(2);
|
|
I.addOperand(InxOp); // set IndexReg
|
|
InxOp.ChangeToImmediate(1); // set Scale
|
|
MIB.addImm(0).addReg(0);
|
|
}
|
|
|
|
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
|
|
}
|
|
|
|
bool X86InstructionSelector::selectGlobalValue(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE) &&
|
|
"unexpected instruction");
|
|
|
|
auto GV = I.getOperand(1).getGlobal();
|
|
if (GV->isThreadLocal()) {
|
|
return false; // TODO: we don't support TLS yet.
|
|
}
|
|
|
|
// Can't handle alternate code models yet.
|
|
if (TM.getCodeModel() != CodeModel::Small)
|
|
return false;
|
|
|
|
X86AddressMode AM;
|
|
AM.GV = GV;
|
|
AM.GVOpFlags = STI.classifyGlobalReference(GV);
|
|
|
|
// TODO: The ABI requires an extra load. not supported yet.
|
|
if (isGlobalStubReference(AM.GVOpFlags))
|
|
return false;
|
|
|
|
// TODO: This reference is relative to the pic base. not supported yet.
|
|
if (isGlobalRelativeToPICBase(AM.GVOpFlags))
|
|
return false;
|
|
|
|
if (STI.isPICStyleRIPRel()) {
|
|
// Use rip-relative addressing.
|
|
assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
|
|
AM.Base.Reg = X86::RIP;
|
|
}
|
|
|
|
const unsigned DefReg = I.getOperand(0).getReg();
|
|
LLT Ty = MRI.getType(DefReg);
|
|
unsigned NewOpc = getLeaOP(Ty, STI);
|
|
|
|
I.setDesc(TII.get(NewOpc));
|
|
MachineInstrBuilder MIB(MF, I);
|
|
|
|
I.RemoveOperand(1);
|
|
addFullAddress(MIB, AM);
|
|
|
|
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
|
|
}
|
|
|
|
bool X86InstructionSelector::selectConstant(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_CONSTANT) &&
|
|
"unexpected instruction");
|
|
|
|
const unsigned DefReg = I.getOperand(0).getReg();
|
|
LLT Ty = MRI.getType(DefReg);
|
|
|
|
if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID)
|
|
return false;
|
|
|
|
uint64_t Val = 0;
|
|
if (I.getOperand(1).isCImm()) {
|
|
Val = I.getOperand(1).getCImm()->getZExtValue();
|
|
I.getOperand(1).ChangeToImmediate(Val);
|
|
} else if (I.getOperand(1).isImm()) {
|
|
Val = I.getOperand(1).getImm();
|
|
} else
|
|
llvm_unreachable("Unsupported operand type.");
|
|
|
|
unsigned NewOpc;
|
|
switch (Ty.getSizeInBits()) {
|
|
case 8:
|
|
NewOpc = X86::MOV8ri;
|
|
break;
|
|
case 16:
|
|
NewOpc = X86::MOV16ri;
|
|
break;
|
|
case 32:
|
|
NewOpc = X86::MOV32ri;
|
|
break;
|
|
case 64:
|
|
// TODO: in case isUInt<32>(Val), X86::MOV32ri can be used
|
|
if (isInt<32>(Val))
|
|
NewOpc = X86::MOV64ri32;
|
|
else
|
|
NewOpc = X86::MOV64ri;
|
|
break;
|
|
default:
|
|
llvm_unreachable("Can't select G_CONSTANT, unsupported type.");
|
|
}
|
|
|
|
I.setDesc(TII.get(NewOpc));
|
|
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
|
|
}
|
|
|
|
bool X86InstructionSelector::selectTrunc(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_TRUNC) && "unexpected instruction");
|
|
|
|
const unsigned DstReg = I.getOperand(0).getReg();
|
|
const unsigned SrcReg = I.getOperand(1).getReg();
|
|
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const LLT SrcTy = MRI.getType(SrcReg);
|
|
|
|
const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
|
|
const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
|
|
|
|
if (DstRB.getID() != SrcRB.getID()) {
|
|
DEBUG(dbgs() << "G_TRUNC input/output on different banks\n");
|
|
return false;
|
|
}
|
|
|
|
if (DstRB.getID() != X86::GPRRegBankID)
|
|
return false;
|
|
|
|
const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
|
|
if (!DstRC)
|
|
return false;
|
|
|
|
const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
|
|
if (!SrcRC)
|
|
return false;
|
|
|
|
unsigned SubIdx;
|
|
if (DstRC == SrcRC) {
|
|
// Nothing to be done
|
|
SubIdx = X86::NoSubRegister;
|
|
} else if (DstRC == &X86::GR32RegClass) {
|
|
SubIdx = X86::sub_32bit;
|
|
} else if (DstRC == &X86::GR16RegClass) {
|
|
SubIdx = X86::sub_16bit;
|
|
} else if (DstRC == &X86::GR8RegClass) {
|
|
SubIdx = X86::sub_8bit;
|
|
} else {
|
|
return false;
|
|
}
|
|
|
|
SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
|
|
|
|
if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
|
|
!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
|
|
DEBUG(dbgs() << "Failed to constrain G_TRUNC\n");
|
|
return false;
|
|
}
|
|
|
|
I.getOperand(1).setSubReg(SubIdx);
|
|
|
|
I.setDesc(TII.get(X86::COPY));
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::selectZext(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_ZEXT) && "unexpected instruction");
|
|
|
|
const unsigned DstReg = I.getOperand(0).getReg();
|
|
const unsigned SrcReg = I.getOperand(1).getReg();
|
|
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const LLT SrcTy = MRI.getType(SrcReg);
|
|
|
|
if (SrcTy != LLT::scalar(1))
|
|
return false;
|
|
|
|
unsigned AndOpc;
|
|
if (DstTy == LLT::scalar(8))
|
|
AndOpc = X86::AND8ri;
|
|
else if (DstTy == LLT::scalar(16))
|
|
AndOpc = X86::AND16ri8;
|
|
else if (DstTy == LLT::scalar(32))
|
|
AndOpc = X86::AND32ri8;
|
|
else if (DstTy == LLT::scalar(64))
|
|
AndOpc = X86::AND64ri8;
|
|
else
|
|
return false;
|
|
|
|
unsigned DefReg = SrcReg;
|
|
if (DstTy != LLT::scalar(8)) {
|
|
DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
|
|
BuildMI(*I.getParent(), I, I.getDebugLoc(),
|
|
TII.get(TargetOpcode::SUBREG_TO_REG), DefReg)
|
|
.addImm(0)
|
|
.addReg(SrcReg)
|
|
.addImm(X86::sub_8bit);
|
|
}
|
|
|
|
MachineInstr &AndInst =
|
|
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg)
|
|
.addReg(DefReg)
|
|
.addImm(1);
|
|
|
|
constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI);
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::selectAnyext(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_ANYEXT) && "unexpected instruction");
|
|
|
|
const unsigned DstReg = I.getOperand(0).getReg();
|
|
const unsigned SrcReg = I.getOperand(1).getReg();
|
|
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const LLT SrcTy = MRI.getType(SrcReg);
|
|
|
|
const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
|
|
const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
|
|
|
|
assert(DstRB.getID() == SrcRB.getID() &&
|
|
"G_ANYEXT input/output on different banks\n");
|
|
|
|
assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
|
|
"G_ANYEXT incorrect operand size");
|
|
|
|
if (DstRB.getID() != X86::GPRRegBankID)
|
|
return false;
|
|
|
|
const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
|
|
const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
|
|
|
|
if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
|
|
!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
|
|
DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
|
|
<< " operand\n");
|
|
return false;
|
|
}
|
|
|
|
if (SrcRC == DstRC) {
|
|
I.setDesc(TII.get(X86::COPY));
|
|
return true;
|
|
}
|
|
|
|
BuildMI(*I.getParent(), I, I.getDebugLoc(),
|
|
TII.get(TargetOpcode::SUBREG_TO_REG))
|
|
.addDef(DstReg)
|
|
.addImm(0)
|
|
.addReg(SrcReg)
|
|
.addImm(getSubRegIndex(SrcRC));
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::selectCmp(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_ICMP) && "unexpected instruction");
|
|
|
|
X86::CondCode CC;
|
|
bool SwapArgs;
|
|
std::tie(CC, SwapArgs) = X86::getX86ConditionCode(
|
|
(CmpInst::Predicate)I.getOperand(1).getPredicate());
|
|
unsigned OpSet = X86::getSETFromCond(CC);
|
|
|
|
unsigned LHS = I.getOperand(2).getReg();
|
|
unsigned RHS = I.getOperand(3).getReg();
|
|
|
|
if (SwapArgs)
|
|
std::swap(LHS, RHS);
|
|
|
|
unsigned OpCmp;
|
|
LLT Ty = MRI.getType(LHS);
|
|
|
|
switch (Ty.getSizeInBits()) {
|
|
default:
|
|
return false;
|
|
case 8:
|
|
OpCmp = X86::CMP8rr;
|
|
break;
|
|
case 16:
|
|
OpCmp = X86::CMP16rr;
|
|
break;
|
|
case 32:
|
|
OpCmp = X86::CMP32rr;
|
|
break;
|
|
case 64:
|
|
OpCmp = X86::CMP64rr;
|
|
break;
|
|
}
|
|
|
|
MachineInstr &CmpInst =
|
|
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
|
|
.addReg(LHS)
|
|
.addReg(RHS);
|
|
|
|
MachineInstr &SetInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
|
|
TII.get(OpSet), I.getOperand(0).getReg());
|
|
|
|
constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
|
|
constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI);
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::selectUadde(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_UADDE) && "unexpected instruction");
|
|
|
|
const unsigned DstReg = I.getOperand(0).getReg();
|
|
const unsigned CarryOutReg = I.getOperand(1).getReg();
|
|
const unsigned Op0Reg = I.getOperand(2).getReg();
|
|
const unsigned Op1Reg = I.getOperand(3).getReg();
|
|
unsigned CarryInReg = I.getOperand(4).getReg();
|
|
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
|
|
if (DstTy != LLT::scalar(32))
|
|
return false;
|
|
|
|
// find CarryIn def instruction.
|
|
MachineInstr *Def = MRI.getVRegDef(CarryInReg);
|
|
while (Def->getOpcode() == TargetOpcode::G_TRUNC) {
|
|
CarryInReg = Def->getOperand(1).getReg();
|
|
Def = MRI.getVRegDef(CarryInReg);
|
|
}
|
|
|
|
unsigned Opcode;
|
|
if (Def->getOpcode() == TargetOpcode::G_UADDE) {
|
|
// carry set by prev ADD.
|
|
|
|
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), X86::EFLAGS)
|
|
.addReg(CarryInReg);
|
|
|
|
if (!RBI.constrainGenericRegister(CarryInReg, X86::GR32RegClass, MRI))
|
|
return false;
|
|
|
|
Opcode = X86::ADC32rr;
|
|
} else if (auto val = getConstantVRegVal(CarryInReg, MRI)) {
|
|
// carry is constant, support only 0.
|
|
if (*val != 0)
|
|
return false;
|
|
|
|
Opcode = X86::ADD32rr;
|
|
} else
|
|
return false;
|
|
|
|
MachineInstr &AddInst =
|
|
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg)
|
|
.addReg(Op0Reg)
|
|
.addReg(Op1Reg);
|
|
|
|
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg)
|
|
.addReg(X86::EFLAGS);
|
|
|
|
if (!constrainSelectedInstRegOperands(AddInst, TII, TRI, RBI) ||
|
|
!RBI.constrainGenericRegister(CarryOutReg, X86::GR32RegClass, MRI))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::selectExtract(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_EXTRACT) &&
|
|
"unexpected instruction");
|
|
|
|
const unsigned DstReg = I.getOperand(0).getReg();
|
|
const unsigned SrcReg = I.getOperand(1).getReg();
|
|
int64_t Index = I.getOperand(2).getImm();
|
|
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const LLT SrcTy = MRI.getType(SrcReg);
|
|
|
|
// Meanwile handle vector type only.
|
|
if (!DstTy.isVector())
|
|
return false;
|
|
|
|
if (Index % DstTy.getSizeInBits() != 0)
|
|
return false; // Not extract subvector.
|
|
|
|
if (Index == 0) {
|
|
// Replace by extract subreg copy.
|
|
if (!emitExtractSubreg(DstReg, SrcReg, I, MRI, MF))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool HasAVX = STI.hasAVX();
|
|
bool HasAVX512 = STI.hasAVX512();
|
|
bool HasVLX = STI.hasVLX();
|
|
|
|
if (SrcTy.getSizeInBits() == 256 && DstTy.getSizeInBits() == 128) {
|
|
if (HasVLX)
|
|
I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
|
|
else if (HasAVX)
|
|
I.setDesc(TII.get(X86::VEXTRACTF128rr));
|
|
else
|
|
return false;
|
|
} else if (SrcTy.getSizeInBits() == 512 && HasAVX512) {
|
|
if (DstTy.getSizeInBits() == 128)
|
|
I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr));
|
|
else if (DstTy.getSizeInBits() == 256)
|
|
I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr));
|
|
else
|
|
return false;
|
|
} else
|
|
return false;
|
|
|
|
// Convert to X86 VEXTRACT immediate.
|
|
Index = Index / DstTy.getSizeInBits();
|
|
I.getOperand(2).setImm(Index);
|
|
|
|
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
|
|
}
|
|
|
|
bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg,
|
|
MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const LLT SrcTy = MRI.getType(SrcReg);
|
|
unsigned SubIdx = X86::NoSubRegister;
|
|
|
|
if (!DstTy.isVector() || !SrcTy.isVector())
|
|
return false;
|
|
|
|
assert(SrcTy.getSizeInBits() > DstTy.getSizeInBits() &&
|
|
"Incorrect Src/Dst register size");
|
|
|
|
if (DstTy.getSizeInBits() == 128)
|
|
SubIdx = X86::sub_xmm;
|
|
else if (DstTy.getSizeInBits() == 256)
|
|
SubIdx = X86::sub_ymm;
|
|
else
|
|
return false;
|
|
|
|
const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
|
|
const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
|
|
|
|
SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
|
|
|
|
if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
|
|
!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
|
|
DEBUG(dbgs() << "Failed to constrain G_TRUNC\n");
|
|
return false;
|
|
}
|
|
|
|
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
|
|
.addReg(SrcReg, 0, SubIdx);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg,
|
|
MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const LLT SrcTy = MRI.getType(SrcReg);
|
|
unsigned SubIdx = X86::NoSubRegister;
|
|
|
|
// TODO: support scalar types
|
|
if (!DstTy.isVector() || !SrcTy.isVector())
|
|
return false;
|
|
|
|
assert(SrcTy.getSizeInBits() < DstTy.getSizeInBits() &&
|
|
"Incorrect Src/Dst register size");
|
|
|
|
if (SrcTy.getSizeInBits() == 128)
|
|
SubIdx = X86::sub_xmm;
|
|
else if (SrcTy.getSizeInBits() == 256)
|
|
SubIdx = X86::sub_ymm;
|
|
else
|
|
return false;
|
|
|
|
const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
|
|
const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
|
|
|
|
if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
|
|
!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
|
|
DEBUG(dbgs() << "Failed to constrain INSERT_SUBREG\n");
|
|
return false;
|
|
}
|
|
|
|
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY))
|
|
.addReg(DstReg, RegState::DefineNoRead, SubIdx)
|
|
.addReg(SrcReg);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::selectInsert(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_INSERT) && "unexpected instruction");
|
|
|
|
const unsigned DstReg = I.getOperand(0).getReg();
|
|
const unsigned SrcReg = I.getOperand(1).getReg();
|
|
const unsigned InsertReg = I.getOperand(2).getReg();
|
|
int64_t Index = I.getOperand(3).getImm();
|
|
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const LLT InsertRegTy = MRI.getType(InsertReg);
|
|
|
|
// Meanwile handle vector type only.
|
|
if (!DstTy.isVector())
|
|
return false;
|
|
|
|
if (Index % InsertRegTy.getSizeInBits() != 0)
|
|
return false; // Not insert subvector.
|
|
|
|
if (Index == 0 && MRI.getVRegDef(SrcReg)->isImplicitDef()) {
|
|
// Replace by subreg copy.
|
|
if (!emitInsertSubreg(DstReg, InsertReg, I, MRI, MF))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool HasAVX = STI.hasAVX();
|
|
bool HasAVX512 = STI.hasAVX512();
|
|
bool HasVLX = STI.hasVLX();
|
|
|
|
if (DstTy.getSizeInBits() == 256 && InsertRegTy.getSizeInBits() == 128) {
|
|
if (HasVLX)
|
|
I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
|
|
else if (HasAVX)
|
|
I.setDesc(TII.get(X86::VINSERTF128rr));
|
|
else
|
|
return false;
|
|
} else if (DstTy.getSizeInBits() == 512 && HasAVX512) {
|
|
if (InsertRegTy.getSizeInBits() == 128)
|
|
I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
|
|
else if (InsertRegTy.getSizeInBits() == 256)
|
|
I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
|
|
else
|
|
return false;
|
|
} else
|
|
return false;
|
|
|
|
// Convert to X86 VINSERT immediate.
|
|
Index = Index / InsertRegTy.getSizeInBits();
|
|
|
|
I.getOperand(3).setImm(Index);
|
|
|
|
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
|
|
}
|
|
|
|
bool X86InstructionSelector::selectUnmergeValues(
|
|
MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF,
|
|
CodeGenCoverage &CoverageInfo) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_UNMERGE_VALUES) &&
|
|
"unexpected instruction");
|
|
|
|
// Split to extracts.
|
|
unsigned NumDefs = I.getNumOperands() - 1;
|
|
unsigned SrcReg = I.getOperand(NumDefs).getReg();
|
|
unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
|
|
|
|
for (unsigned Idx = 0; Idx < NumDefs; ++Idx) {
|
|
MachineInstr &ExtrInst =
|
|
*BuildMI(*I.getParent(), I, I.getDebugLoc(),
|
|
TII.get(TargetOpcode::G_EXTRACT), I.getOperand(Idx).getReg())
|
|
.addReg(SrcReg)
|
|
.addImm(Idx * DefSize);
|
|
|
|
if (!select(ExtrInst, CoverageInfo))
|
|
return false;
|
|
}
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::selectMergeValues(
|
|
MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF,
|
|
CodeGenCoverage &CoverageInfo) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_MERGE_VALUES) &&
|
|
"unexpected instruction");
|
|
|
|
// Split to inserts.
|
|
unsigned DstReg = I.getOperand(0).getReg();
|
|
unsigned SrcReg0 = I.getOperand(1).getReg();
|
|
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const LLT SrcTy = MRI.getType(SrcReg0);
|
|
unsigned SrcSize = SrcTy.getSizeInBits();
|
|
|
|
const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
|
|
|
|
// For the first src use insertSubReg.
|
|
unsigned DefReg = MRI.createGenericVirtualRegister(DstTy);
|
|
MRI.setRegBank(DefReg, RegBank);
|
|
if (!emitInsertSubreg(DefReg, I.getOperand(1).getReg(), I, MRI, MF))
|
|
return false;
|
|
|
|
for (unsigned Idx = 2; Idx < I.getNumOperands(); ++Idx) {
|
|
unsigned Tmp = MRI.createGenericVirtualRegister(DstTy);
|
|
MRI.setRegBank(Tmp, RegBank);
|
|
|
|
MachineInstr &InsertInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
|
|
TII.get(TargetOpcode::G_INSERT), Tmp)
|
|
.addReg(DefReg)
|
|
.addReg(I.getOperand(Idx).getReg())
|
|
.addImm((Idx - 1) * SrcSize);
|
|
|
|
DefReg = Tmp;
|
|
|
|
if (!select(InsertInst, CoverageInfo))
|
|
return false;
|
|
}
|
|
|
|
MachineInstr &CopyInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
|
|
TII.get(TargetOpcode::COPY), DstReg)
|
|
.addReg(DefReg);
|
|
|
|
if (!select(CopyInst, CoverageInfo))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::selectCondBranch(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_BRCOND) && "unexpected instruction");
|
|
|
|
const unsigned CondReg = I.getOperand(0).getReg();
|
|
MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
|
|
|
|
MachineInstr &TestInst =
|
|
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
|
|
.addReg(CondReg)
|
|
.addImm(1);
|
|
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JNE_1))
|
|
.addMBB(DestMBB);
|
|
|
|
constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::materializeFP(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_FCONSTANT) &&
|
|
"unexpected instruction");
|
|
|
|
// Can't handle alternate code models yet.
|
|
CodeModel::Model CM = TM.getCodeModel();
|
|
if (CM != CodeModel::Small && CM != CodeModel::Large)
|
|
return false;
|
|
|
|
const unsigned DstReg = I.getOperand(0).getReg();
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
|
|
unsigned Align = DstTy.getSizeInBits();
|
|
const DebugLoc &DbgLoc = I.getDebugLoc();
|
|
|
|
unsigned Opc = getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Align);
|
|
|
|
// Create the load from the constant pool.
|
|
const ConstantFP *CFP = I.getOperand(1).getFPImm();
|
|
unsigned CPI = MF.getConstantPool()->getConstantPoolIndex(CFP, Align);
|
|
MachineInstr *LoadInst = nullptr;
|
|
unsigned char OpFlag = STI.classifyLocalReference(nullptr);
|
|
|
|
if (CM == CodeModel::Large && STI.is64Bit()) {
|
|
// Under X86-64 non-small code model, GV (and friends) are 64-bits, so
|
|
// they cannot be folded into immediate fields.
|
|
|
|
unsigned AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass);
|
|
BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
|
|
.addConstantPoolIndex(CPI, 0, OpFlag);
|
|
|
|
MachineMemOperand *MMO = MF.getMachineMemOperand(
|
|
MachinePointerInfo::getConstantPool(MF), MachineMemOperand::MOLoad,
|
|
MF.getDataLayout().getPointerSize(), Align);
|
|
|
|
LoadInst =
|
|
addDirectMem(BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg),
|
|
AddrReg)
|
|
.addMemOperand(MMO);
|
|
|
|
} else if (CM == CodeModel::Small || !STI.is64Bit()) {
|
|
// Handle the case when globals fit in our immediate field.
|
|
// This is true for X86-32 always and X86-64 when in -mcmodel=small mode.
|
|
|
|
// x86-32 PIC requires a PIC base register for constant pools.
|
|
unsigned PICBase = 0;
|
|
if (OpFlag == X86II::MO_PIC_BASE_OFFSET || OpFlag == X86II::MO_GOTOFF) {
|
|
// PICBase can be allocated by TII.getGlobalBaseReg(&MF).
|
|
// In DAGISEL the code that initialize it generated by the CGBR pass.
|
|
return false; // TODO support the mode.
|
|
} else if (STI.is64Bit() && TM.getCodeModel() == CodeModel::Small)
|
|
PICBase = X86::RIP;
|
|
|
|
LoadInst = addConstantPoolReference(
|
|
BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), CPI, PICBase,
|
|
OpFlag);
|
|
} else
|
|
return false;
|
|
|
|
constrainSelectedInstRegOperands(*LoadInst, TII, TRI, RBI);
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool X86InstructionSelector::selectImplicitDefOrPHI(
|
|
MachineInstr &I, MachineRegisterInfo &MRI) const {
|
|
assert((I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
|
|
I.getOpcode() == TargetOpcode::G_PHI) &&
|
|
"unexpected instruction");
|
|
|
|
unsigned DstReg = I.getOperand(0).getReg();
|
|
|
|
if (!MRI.getRegClassOrNull(DstReg)) {
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const TargetRegisterClass *RC = getRegClass(DstTy, DstReg, MRI);
|
|
|
|
if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
|
|
DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
|
|
<< " operand\n");
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
|
|
I.setDesc(TII.get(X86::IMPLICIT_DEF));
|
|
else
|
|
I.setDesc(TII.get(X86::PHI));
|
|
|
|
return true;
|
|
}
|
|
|
|
InstructionSelector *
|
|
llvm::createX86InstructionSelector(const X86TargetMachine &TM,
|
|
X86Subtarget &Subtarget,
|
|
X86RegisterBankInfo &RBI) {
|
|
return new X86InstructionSelector(TM, Subtarget, RBI);
|
|
}
|