Chad Rosier f8df4f4e3b [avx] Define the _mm256_loadu2_xxx and _mm256_storeu2_xxx intrinsics. ... From the Intel Optimization Reference Manual, Section 11.6.2. When data cannot be aligned or alignment is not known, 16-byte memory accesses may provide better performance. rdar://11076953 llvm-svn: 153091		2012-03-20 16:40:00 +00:00
clang	[avx] Define the _mm256_loadu2_xxx and _mm256_storeu2_xxx intrinsics.	2012-03-20 16:40:00 +00:00
compiler-rt	[ASan] get rid of setjmp.h header in interceptors	2012-03-20 11:40:09 +00:00
debuginfo-tests	Revert previous patch as the corresponding clang patch was reverted.	2012-01-26 07:01:33 +00:00
libclc	Switch to BSD/MIT dual license.	2012-02-22 04:47:39 +00:00
libcxx	Allow libc++ to be built with CMake from within the LLVM tree. The libc++ part is just some renaming as the variable was already in use, conflicting with something else in the LLVM tree. Contributed by Ruben Van Boxem.	2012-03-19 15:40:23 +00:00
libcxxabi	I would really like to write the handlers in terms of C++11 atomics. This would give us the best performance, portablity, and safety tradeoff. Unfortunately I can not yet do that. So I've put the desired code in comments, and reverted the handler getters to the slower but safer legacy atomic intrinsics.	2012-03-19 16:56:51 +00:00
lld	Add more details about file formats. Fix whitespace.	2012-03-16 20:03:05 +00:00
lldb	<rdar://problem/11078937>	2012-03-20 02:15:45 +00:00
llvm	The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.	2012-03-20 15:54:56 +00:00
polly	ScheduleOptimizer: Remove forgotten debug output	2012-03-16 18:45:10 +00:00