Oliver Stannard 65f7bc5bf0 [Assembler] Report multiple near misses for invalid instructions ... The current table-generated assembly instruction matcher returns a 64-bit error code when matching fails. Since multiple instruction encodings with the same mnemonic can fail for different reasons, it uses some heuristics to decide which message is important. This heuristic does not work well for targets that have many encodings with the same mnemonic but different operands, or which have different versions of instructions controlled by subtarget features, as it is hard to know which encoding the user was intending to use. Instead of trying to improve the heuristic in the table-generated matcher, this patch changes it to report a list of near-miss encodings. This list contains an entry for each encoding with the correct mnemonic, but with exactly one thing preventing it from being valid. This thing could be a single invalid operand, a missing target feature or a failed target-specific validation function. The target-specific assembly parser can then report an error message giving multiple options for instruction variants that the user may have been trying to use. For example, I am working on a patch to use this for ARM, which can give this error for an invalid instruction for ARMv6-M: <stdin>:8:3: error: invalid instruction, multiple near-miss encodings found adds r0, r1, #0x8 ^ <stdin>:8:3: note: for one encoding: instruction requires: thumb2 adds r0, r1, #0x8 ^ <stdin>:8:16: note: for one encoding: expected an integer in range [0, 7] adds r0, r1, #0x8 ^ <stdin>:8:16: note: for one encoding: expected a register in range [r0, r7] adds r0, r1, #0x8 ^ This also allows the target-specific assembly parser to apply its own heuristics to suppress some errors. For example, the error "instruction requires: arm-mode" is never going to be useful when targeting an M-profile architecture (which does not have ARM mode). This patch just adds the target-independent mechanism for doing this, all targets still use the old mechanism. I've added a bit in the AsmParser tablegen class to allow targets to switch to this new mechanism. To use this, the target-specific assembly parser will have to be modified for the change in signature of MatchInstructionImpl, and to report errors based on the list of near-misses. Differential revision: https://reviews.llvm.org/D27620 llvm-svn: 314774		2017-10-03 09:33:12 +00:00
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llvm	[Assembler] Report multiple near misses for invalid instructions	2017-10-03 09:33:12 +00:00
llvm-c	[ORC] Hook up the LLVMOrcAddObjectFile function in the Orc C Bindings.	2017-09-17 03:25:03 +00:00