Luke Cheeseman b5c627aba8 When lowering vector shifts a check is performed to see if the value to shift by ... is an immediate, in this check the value is negated and stored in and int64_t. The value can be -2^63 yet the result cannot be stored in an int64_t and this gives some undefined behaviour causing failures. The negation is only necessary when the values is within a certain range and so it should not need to negate -2^63, this patch introduces this and also a regression test. Differential Revision: http://reviews.llvm.org/D11408 llvm-svn: 243100		2015-07-24 09:31:48 +00:00
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AArch64	This patch eanble register coalescing to coalesce the following:	2015-07-23 19:24:53 +00:00
AMDGPU	AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops	2015-07-20 14:28:41 +00:00
ARM	When lowering vector shifts a check is performed to see if the value to shift by	2015-07-24 09:31:48 +00:00
BPF	[bpf] rename triple names bpf_be -> bpfeb	2015-06-05 16:11:14 +00:00
CPP	[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction	2015-04-16 23:24:18 +00:00
Generic	Targets: commonize some stack realignment code	2015-07-20 22:51:32 +00:00
Hexagon	[Hexagon] Generate MUX from conditional transfers when dot-new not possible	2015-07-20 21:23:25 +00:00
Inputs	IR: Give 'DI' prefix to debug info metadata	2015-04-29 16:38:44 +00:00
MIR	MIR Serialization: Serialize the '.cfi_offset' CFI instruction.	2015-07-23 23:09:07 +00:00
MSP430	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
Mips	[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)	2015-07-15 08:39:35 +00:00
NVPTX	[BranchFolding] do not iterate the aliases of virtual registers	2015-07-22 04:16:52 +00:00
PowerPC	Clean up function attributes on PPC fast-isel tests.	2015-07-24 01:07:50 +00:00
SPARC	[SPARC] Cleanup handling of the Y/ASR registers.	2015-07-08 16:25:12 +00:00
SystemZ	[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load	2015-05-05 19:34:10 +00:00
Thumb	[ARM] Make the frame lowering code ready for shrink-wrapping.	2015-07-22 16:34:37 +00:00
Thumb2	ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2	2015-07-21 00:18:59 +00:00
WebAssembly	WebAssembly: test that valid -mcpu flags are accepted.	2015-07-23 23:00:04 +00:00
WinEH	[WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name	2015-07-13 17:55:14 +00:00
X86	fix crash in machine trace metrics due to processing dbg_value instructions (PR24199)	2015-07-23 22:56:53 +00:00
XCore	Move the personality function from LandingPadInst to Function	2015-06-17 20:52:32 +00:00