forked from OSchip/llvm-project
744 lines
21 KiB
LLVM
744 lines
21 KiB
LLVM
; RUN: opt < %s -basicaa -licm -S | FileCheck %s
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; RUN: opt < %s -debugify -basicaa -licm -S | FileCheck %s -check-prefix=DEBUGIFY
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; RUN: opt < %s -basicaa -licm -S -enable-mssa-loop-dependency=true -verify-memoryssa | FileCheck %s
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declare i32 @strlen(i8*) readonly nounwind
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declare void @foo()
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; Sink readonly function.
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define i32 @test1(i8* %P) {
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br label %Loop
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Loop: ; preds = %Loop, %0
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%A = call i32 @strlen( i8* %P ) readonly
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br i1 false, label %Loop, label %Out
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Out: ; preds = %Loop
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ret i32 %A
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; CHECK-LABEL: @test1(
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; CHECK: Out:
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; CHECK-NEXT: call i32 @strlen
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; CHECK-NEXT: ret i32 %A
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}
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declare double @sin(double) readnone nounwind
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; Sink readnone function out of loop with unknown memory behavior.
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define double @test2(double %X) {
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br label %Loop
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Loop: ; preds = %Loop, %0
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call void @foo( )
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%A = call double @sin( double %X ) readnone
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br i1 true, label %Loop, label %Out
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Out: ; preds = %Loop
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ret double %A
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; CHECK-LABEL: @test2(
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; CHECK: Out:
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; CHECK-NEXT: call double @sin
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; CHECK-NEXT: ret double %A
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}
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; FIXME: Should be able to sink this case
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define i32 @test2b(i32 %X) {
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br label %Loop
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Loop: ; preds = %Loop, %0
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call void @foo( )
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%A = sdiv i32 10, %X
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br i1 true, label %Loop, label %Out
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Out: ; preds = %Loop
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ret i32 %A
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; CHECK-LABEL: @test2b(
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; CHECK: Out:
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; CHECK-NEXT: sdiv
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; CHECK-NEXT: ret i32 %A
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}
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define double @test2c(double* %P) {
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br label %Loop
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Loop: ; preds = %Loop, %0
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call void @foo( )
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%A = load double, double* %P, !invariant.load !{}
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br i1 true, label %Loop, label %Out
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Out: ; preds = %Loop
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ret double %A
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; CHECK-LABEL: @test2c(
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; CHECK: Out:
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; CHECK-NEXT: load double
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; CHECK-NEXT: ret double %A
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}
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; This testcase checks to make sure the sinker does not cause problems with
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; critical edges.
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define void @test3() {
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Entry:
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br i1 false, label %Loop, label %Exit
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Loop:
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%X = add i32 0, 1
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br i1 false, label %Loop, label %Exit
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Exit:
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%Y = phi i32 [ 0, %Entry ], [ %X, %Loop ]
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ret void
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; CHECK-LABEL: @test3(
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; CHECK: Exit.loopexit:
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; CHECK-NEXT: %X.le = add i32 0, 1
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; CHECK-NEXT: br label %Exit
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}
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; If the result of an instruction is only used outside of the loop, sink
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; the instruction to the exit blocks instead of executing it on every
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; iteration of the loop.
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;
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define i32 @test4(i32 %N) {
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Entry:
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br label %Loop
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Loop: ; preds = %Loop, %Entry
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%N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ]
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%tmp.6 = mul i32 %N, %N_addr.0.pn ; <i32> [#uses=1]
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%tmp.7 = sub i32 %tmp.6, %N ; <i32> [#uses=1]
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%dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1]
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%tmp.1 = icmp ne i32 %N_addr.0.pn, 1 ; <i1> [#uses=1]
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br i1 %tmp.1, label %Loop, label %Out
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Out: ; preds = %Loop
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ret i32 %tmp.7
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; CHECK-LABEL: @test4(
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; CHECK: Out:
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; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn
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; CHECK-NEXT: mul i32 %N, %[[LCSSAPHI]]
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; CHECK-NEXT: sub i32 %tmp.6.le, %N
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; CHECK-NEXT: ret i32
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}
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; To reduce register pressure, if a load is hoistable out of the loop, and the
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; result of the load is only used outside of the loop, sink the load instead of
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; hoisting it!
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;
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@X = global i32 5 ; <i32*> [#uses=1]
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define i32 @test5(i32 %N) {
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Entry:
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br label %Loop
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Loop: ; preds = %Loop, %Entry
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%N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ]
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%tmp.6 = load i32, i32* @X ; <i32> [#uses=1]
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%dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1]
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%tmp.1 = icmp ne i32 %N_addr.0.pn, 1 ; <i1> [#uses=1]
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br i1 %tmp.1, label %Loop, label %Out
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Out: ; preds = %Loop
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ret i32 %tmp.6
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; CHECK-LABEL: @test5(
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; CHECK: Out:
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; CHECK-NEXT: %tmp.6.le = load i32, i32* @X
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; CHECK-NEXT: ret i32 %tmp.6.le
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}
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; The loop sinker was running from the bottom of the loop to the top, causing
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; it to miss opportunities to sink instructions that depended on sinking other
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; instructions from the loop. Instead they got hoisted, which is better than
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; leaving them in the loop, but increases register pressure pointlessly.
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%Ty = type { i32, i32 }
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@X2 = external global %Ty
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define i32 @test6() {
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br label %Loop
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Loop:
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%dead = getelementptr %Ty, %Ty* @X2, i64 0, i32 0
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%sunk2 = load i32, i32* %dead
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br i1 false, label %Loop, label %Out
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Out: ; preds = %Loop
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ret i32 %sunk2
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; CHECK-LABEL: @test6(
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; CHECK: Out:
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; CHECK-NEXT: %dead.le = getelementptr %Ty, %Ty* @X2, i64 0, i32 0
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; CHECK-NEXT: %sunk2.le = load i32, i32* %dead.le
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; CHECK-NEXT: ret i32 %sunk2.le
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}
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; This testcase ensures that we can sink instructions from loops with
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; multiple exits.
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;
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define i32 @test7(i32 %N, i1 %C) {
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Entry:
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br label %Loop
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Loop: ; preds = %ContLoop, %Entry
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%N_addr.0.pn = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ]
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%tmp.6 = mul i32 %N, %N_addr.0.pn
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%tmp.7 = sub i32 %tmp.6, %N ; <i32> [#uses=2]
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%dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1]
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br i1 %C, label %ContLoop, label %Out1
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ContLoop:
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%tmp.1 = icmp ne i32 %N_addr.0.pn, 1
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br i1 %tmp.1, label %Loop, label %Out2
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Out1: ; preds = %Loop
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ret i32 %tmp.7
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Out2: ; preds = %ContLoop
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ret i32 %tmp.7
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; CHECK-LABEL: @test7(
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; CHECK: Out1:
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; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn
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; CHECK-NEXT: mul i32 %N, %[[LCSSAPHI]]
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; CHECK-NEXT: sub i32 %tmp.6.le, %N
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; CHECK-NEXT: ret
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; CHECK: Out2:
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; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn
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; CHECK-NEXT: mul i32 %N, %[[LCSSAPHI]]
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; CHECK-NEXT: sub i32 %tmp.6.le4, %N
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; CHECK-NEXT: ret
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}
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; This testcase checks to make sure we can sink values which are only live on
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; some exits out of the loop, and that we can do so without breaking dominator
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; info.
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define i32 @test8(i1 %C1, i1 %C2, i32* %P, i32* %Q) {
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Entry:
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br label %Loop
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Loop: ; preds = %Cont, %Entry
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br i1 %C1, label %Cont, label %exit1
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Cont: ; preds = %Loop
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%X = load i32, i32* %P ; <i32> [#uses=2]
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store i32 %X, i32* %Q
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%V = add i32 %X, 1 ; <i32> [#uses=1]
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br i1 %C2, label %Loop, label %exit2
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exit1: ; preds = %Loop
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ret i32 0
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exit2: ; preds = %Cont
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ret i32 %V
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; CHECK-LABEL: @test8(
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; CHECK: exit1:
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; CHECK-NEXT: ret i32 0
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; CHECK: exit2:
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; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %X
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; CHECK-NEXT: %V.le = add i32 %[[LCSSAPHI]], 1
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; CHECK-NEXT: ret i32 %V.le
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}
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define void @test9() {
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loopentry.2.i:
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br i1 false, label %no_exit.1.i.preheader, label %loopentry.3.i.preheader
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no_exit.1.i.preheader: ; preds = %loopentry.2.i
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br label %no_exit.1.i
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no_exit.1.i: ; preds = %endif.8.i, %no_exit.1.i.preheader
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br i1 false, label %return.i, label %endif.8.i
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endif.8.i: ; preds = %no_exit.1.i
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%inc.1.i = add i32 0, 1 ; <i32> [#uses=1]
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br i1 false, label %no_exit.1.i, label %loopentry.3.i.preheader.loopexit
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loopentry.3.i.preheader.loopexit: ; preds = %endif.8.i
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br label %loopentry.3.i.preheader
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loopentry.3.i.preheader: ; preds = %loopentry.3.i.preheader.loopexit, %loopentry.2.i
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%arg_num.0.i.ph13000 = phi i32 [ 0, %loopentry.2.i ], [ %inc.1.i, %loopentry.3.i.preheader.loopexit ] ; <i32> [#uses=0]
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ret void
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return.i: ; preds = %no_exit.1.i
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ret void
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; CHECK-LABEL: @test9(
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; CHECK: loopentry.3.i.preheader.loopexit:
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; CHECK-NEXT: %inc.1.i.le = add i32 0, 1
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; CHECK-NEXT: br label %loopentry.3.i.preheader
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}
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; Potentially trapping instructions may be sunk as long as they are guaranteed
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; to be executed.
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define i32 @test10(i32 %N) {
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Entry:
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br label %Loop
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Loop: ; preds = %Loop, %Entry
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%N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ] ; <i32> [#uses=3]
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%tmp.6 = sdiv i32 %N, %N_addr.0.pn ; <i32> [#uses=1]
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%dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1]
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%tmp.1 = icmp ne i32 %N_addr.0.pn, 0 ; <i1> [#uses=1]
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br i1 %tmp.1, label %Loop, label %Out
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Out: ; preds = %Loop
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ret i32 %tmp.6
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; CHECK-LABEL: @test10(
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; CHECK: Out:
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; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn
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; CHECK-NEXT: %tmp.6.le = sdiv i32 %N, %[[LCSSAPHI]]
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; CHECK-NEXT: ret i32 %tmp.6.le
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}
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; Should delete, not sink, dead instructions.
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define void @test11() {
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br label %Loop
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Loop:
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%dead1 = getelementptr %Ty, %Ty* @X2, i64 0, i32 0
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%dead2 = getelementptr %Ty, %Ty* @X2, i64 0, i32 1
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br i1 false, label %Loop, label %Out
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Out:
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ret void
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; CHECK-LABEL: @test11(
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; CHECK: Out:
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; CHECK-NEXT: ret void
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; The GEP in dead1 is adding a zero offset, so the DIExpression can be kept as
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; a "register location".
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; The GEP in dead2 is adding a 4 bytes to the pointer, so the DIExpression is
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; turned into an "implicit location" using DW_OP_stack_value.
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;
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; DEBUGIFY-LABEL: @test11(
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; DEBUGIFY: call void @llvm.dbg.value(metadata %Ty* @X2, metadata {{.*}}, metadata !DIExpression())
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; DEBUGIFY: call void @llvm.dbg.value(metadata %Ty* @X2, metadata {{.*}}, metadata !DIExpression(DW_OP_plus_uconst, 4, DW_OP_stack_value))
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}
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@c = common global [1 x i32] zeroinitializer, align 4
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; Test a *many* way nested loop with multiple exit blocks both of which exit
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; multiple loop nests. This exercises LCSSA corner cases.
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define i32 @PR18753(i1* %a, i1* %b, i1* %c, i1* %d) {
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entry:
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br label %l1.header
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l1.header:
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%iv = phi i64 [ %iv.next, %l1.latch ], [ 0, %entry ]
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%arrayidx.i = getelementptr inbounds [1 x i32], [1 x i32]* @c, i64 0, i64 %iv
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br label %l2.header
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l2.header:
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%x0 = load i1, i1* %c, align 4
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br i1 %x0, label %l1.latch, label %l3.preheader
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l3.preheader:
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br label %l3.header
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l3.header:
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%x1 = load i1, i1* %d, align 4
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br i1 %x1, label %l2.latch, label %l4.preheader
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l4.preheader:
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br label %l4.header
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l4.header:
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%x2 = load i1, i1* %a
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br i1 %x2, label %l3.latch, label %l4.body
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l4.body:
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call void @f(i32* %arrayidx.i)
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%x3 = load i1, i1* %b
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%l = trunc i64 %iv to i32
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br i1 %x3, label %l4.latch, label %exit
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l4.latch:
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call void @g()
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%x4 = load i1, i1* %b, align 4
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br i1 %x4, label %l4.header, label %exit
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l3.latch:
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br label %l3.header
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l2.latch:
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br label %l2.header
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l1.latch:
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%iv.next = add nsw i64 %iv, 1
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br label %l1.header
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exit:
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%lcssa = phi i32 [ %l, %l4.latch ], [ %l, %l4.body ]
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; CHECK-LABEL: @PR18753(
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; CHECK: exit:
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; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i64 [ %iv, %l4.latch ], [ %iv, %l4.body ]
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; CHECK-NEXT: %l.le = trunc i64 %[[LCSSAPHI]] to i32
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; CHECK-NEXT: ret i32 %l.le
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ret i32 %lcssa
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}
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; @test12 moved to sink-promote.ll, as it tests sinking and promotion.
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; Test that we don't crash when trying to sink stores and there's no preheader
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; available (which is used for creating loads that may be used by the SSA
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; updater)
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define void @test13() {
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; CHECK-LABEL: @test13
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br label %lab59
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lab19:
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br i1 undef, label %lab20, label %lab38
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lab20:
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br label %lab60
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lab21:
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br i1 undef, label %lab22, label %lab38
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lab22:
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br label %lab38
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lab38:
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ret void
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lab59:
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indirectbr i8* undef, [label %lab60, label %lab38]
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lab60:
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; CHECK: lab60:
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; CHECK: store
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; CHECK-NEXT: indirectbr
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store i32 2145244101, i32* undef, align 4
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indirectbr i8* undef, [label %lab21, label %lab19]
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}
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; Check if LICM can sink a sinkable instruction the exit blocks through
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; a non-trivially replacable PHI node.
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;
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; CHECK-LABEL: @test14
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; CHECK-LABEL: Loop:
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; CHECK-NOT: mul
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; CHECK-NOT: sub
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;
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; CHECK-LABEL: Out12.split.loop.exit:
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; CHECK: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn, %ContLoop ]
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; CHECK: %[[MUL:.*]] = mul i32 %N, %[[LCSSAPHI]]
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; CHECK: br label %Out12
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;
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; CHECK-LABEL: Out12.split.loop.exit1:
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; CHECK: %[[LCSSAPHI2:.*]] = phi i32 [ %N_addr.0.pn, %Loop ]
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; CHECK: %[[MUL2:.*]] = mul i32 %N, %[[LCSSAPHI2]]
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; CHECK: %[[SUB:.*]] = sub i32 %[[MUL2]], %N
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; CHECK: br label %Out12
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;
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; CHECK-LABEL: Out12:
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; CHECK: phi i32 [ %[[MUL]], %Out12.split.loop.exit ], [ %[[SUB]], %Out12.split.loop.exit1 ]
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define i32 @test14(i32 %N, i32 %N2, i1 %C) {
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Entry:
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br label %Loop
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Loop:
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%N_addr.0.pn = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ]
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%sink.mul = mul i32 %N, %N_addr.0.pn
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%sink.sub = sub i32 %sink.mul, %N
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%dec = add i32 %N_addr.0.pn, -1
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br i1 %C, label %ContLoop, label %Out12
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ContLoop:
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%tmp.1 = icmp ne i32 %N_addr.0.pn, 1
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br i1 %tmp.1, label %Loop, label %Out12
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Out12:
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%tmp = phi i32 [%sink.mul, %ContLoop], [%sink.sub, %Loop]
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ret i32 %tmp
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}
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; In this test, splitting predecessors is not really required because the
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; operations of sinkable instructions (sub and mul) are same. In this case, we
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; can sink the same sinkable operations and modify the PHI to pass the operands
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; to the shared operations. As of now, we split predecessors of non-trivially
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; replicalbe PHIs by default in LICM because all incoming edges of a
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; non-trivially replacable PHI in LCSSA is critical.
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;
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; CHECK-LABEL: @test15
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; CHECK-LABEL: Loop:
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; CHECK-NOT: mul
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; CHECK-NOT: sub
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;
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; CHECK-LABEL: Out12.split.loop.exit:
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; CHECK: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn, %ContLoop ]
|
|
; CHECK: %[[MUL:.*]] = mul i32 %N, %[[LCSSAPHI]]
|
|
; CHECK: %[[SUB:.*]] = sub i32 %[[MUL]], %N2
|
|
; CHECK: br label %Out12
|
|
;
|
|
; CHECK-LABEL: Out12.split.loop.exit1:
|
|
; CHECK: %[[LCSSAPHI2:.*]] = phi i32 [ %N_addr.0.pn, %Loop ]
|
|
; CHECK: %[[MUL2:.*]] = mul i32 %N, %[[LCSSAPHI2]]
|
|
; CHECK: %[[SUB2:.*]] = sub i32 %[[MUL2]], %N
|
|
; CHECK: br label %Out12
|
|
;
|
|
; CHECK-LABEL: Out12:
|
|
; CHECK: phi i32 [ %[[SUB]], %Out12.split.loop.exit ], [ %[[SUB2]], %Out12.split.loop.exit1 ]
|
|
define i32 @test15(i32 %N, i32 %N2, i1 %C) {
|
|
Entry:
|
|
br label %Loop
|
|
Loop:
|
|
%N_addr.0.pn = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ]
|
|
%sink.mul = mul i32 %N, %N_addr.0.pn
|
|
%sink.sub = sub i32 %sink.mul, %N
|
|
%sink.sub2 = sub i32 %sink.mul, %N2
|
|
%dec = add i32 %N_addr.0.pn, -1
|
|
br i1 %C, label %ContLoop, label %Out12
|
|
ContLoop:
|
|
%tmp.1 = icmp ne i32 %N_addr.0.pn, 1
|
|
br i1 %tmp.1, label %Loop, label %Out12
|
|
Out12:
|
|
%tmp = phi i32 [%sink.sub2, %ContLoop], [%sink.sub, %Loop]
|
|
ret i32 %tmp
|
|
}
|
|
|
|
; Sink through a non-trivially replacable PHI node which use the same sinkable
|
|
; instruction multiple times.
|
|
;
|
|
; CHECK-LABEL: @test16
|
|
; CHECK-LABEL: Loop:
|
|
; CHECK-NOT: mul
|
|
;
|
|
; CHECK-LABEL: Out.split.loop.exit:
|
|
; CHECK: %[[PHI:.*]] = phi i32 [ %l2, %ContLoop ]
|
|
; CHECK: br label %Out
|
|
;
|
|
; CHECK-LABEL: Out.split.loop.exit1:
|
|
; CHECK: %[[SINKABLE:.*]] = mul i32 %l2.lcssa, %t.le
|
|
; CHECK: br label %Out
|
|
;
|
|
; CHECK-LABEL: Out:
|
|
; CHECK: %idx = phi i32 [ %[[PHI]], %Out.split.loop.exit ], [ %[[SINKABLE]], %Out.split.loop.exit1 ]
|
|
define i32 @test16(i1 %c, i8** %P, i32* %P2, i64 %V) {
|
|
entry:
|
|
br label %loop.ph
|
|
loop.ph:
|
|
br label %Loop
|
|
Loop:
|
|
%iv = phi i64 [ 0, %loop.ph ], [ %next, %ContLoop ]
|
|
%l2 = call i32 @getv()
|
|
%t = trunc i64 %iv to i32
|
|
%sinkable = mul i32 %l2, %t
|
|
switch i32 %l2, label %ContLoop [
|
|
i32 32, label %Out
|
|
i32 46, label %Out
|
|
i32 95, label %Out
|
|
]
|
|
ContLoop:
|
|
%next = add nuw i64 %iv, 1
|
|
%c1 = call i1 @getc()
|
|
br i1 %c1, label %Loop, label %Out
|
|
Out:
|
|
%idx = phi i32 [ %l2, %ContLoop ], [ %sinkable, %Loop ], [ %sinkable, %Loop ], [ %sinkable, %Loop ]
|
|
ret i32 %idx
|
|
}
|
|
|
|
; Sink a sinkable instruction through multiple non-trivially replacable PHIs in
|
|
; differect exit blocks.
|
|
;
|
|
; CHECK-LABEL: @test17
|
|
; CHECK-LABEL: Loop:
|
|
; CHECK-NOT: mul
|
|
;
|
|
; CHECK-LABEL:OutA.split.loop.exit{{.*}}:
|
|
; CHECK: %[[OP1:.*]] = phi i32 [ %N_addr.0.pn, %ContLoop1 ]
|
|
; CHECK: %[[SINKABLE:.*]] = mul i32 %N, %[[OP1]]
|
|
; CHECK: br label %OutA
|
|
;
|
|
; CHECK-LABEL:OutA:
|
|
; CHECK: phi i32{{.*}}[ %[[SINKABLE]], %OutA.split.loop.exit{{.*}} ]
|
|
;
|
|
; CHECK-LABEL:OutB.split.loop.exit{{.*}}:
|
|
; CHECK: %[[OP2:.*]] = phi i32 [ %N_addr.0.pn, %ContLoop2 ]
|
|
; CHECK: %[[SINKABLE2:.*]] = mul i32 %N, %[[OP2]]
|
|
; CHECK: br label %OutB
|
|
;
|
|
; CHECK-LABEL:OutB:
|
|
; CHECK: phi i32 {{.*}}[ %[[SINKABLE2]], %OutB.split.loop.exit{{.*}} ]
|
|
define i32 @test17(i32 %N, i32 %N2) {
|
|
Entry:
|
|
br label %Loop
|
|
Loop:
|
|
%N_addr.0.pn = phi i32 [ %dec, %ContLoop3 ], [ %N, %Entry ]
|
|
%sink.mul = mul i32 %N, %N_addr.0.pn
|
|
%c0 = call i1 @getc()
|
|
br i1 %c0 , label %ContLoop1, label %OutA
|
|
ContLoop1:
|
|
%c1 = call i1 @getc()
|
|
br i1 %c1, label %ContLoop2, label %OutA
|
|
|
|
ContLoop2:
|
|
%c2 = call i1 @getc()
|
|
br i1 %c2, label %ContLoop3, label %OutB
|
|
ContLoop3:
|
|
%c3 = call i1 @getc()
|
|
%dec = add i32 %N_addr.0.pn, -1
|
|
br i1 %c3, label %Loop, label %OutB
|
|
OutA:
|
|
%tmp1 = phi i32 [%sink.mul, %ContLoop1], [%N2, %Loop]
|
|
br label %Out12
|
|
OutB:
|
|
%tmp2 = phi i32 [%sink.mul, %ContLoop2], [%dec, %ContLoop3]
|
|
br label %Out12
|
|
Out12:
|
|
%tmp = phi i32 [%tmp1, %OutA], [%tmp2, %OutB]
|
|
ret i32 %tmp
|
|
}
|
|
|
|
|
|
; Sink a sinkable instruction through both trivially and non-trivially replacable PHIs.
|
|
;
|
|
; CHECK-LABEL: @test18
|
|
; CHECK-LABEL: Loop:
|
|
; CHECK-NOT: mul
|
|
; CHECK-NOT: sub
|
|
;
|
|
; CHECK-LABEL:Out12.split.loop.exit:
|
|
; CHECK: %[[OP:.*]] = phi i32 [ %iv, %ContLoop ]
|
|
; CHECK: %[[DEC:.*]] = phi i32 [ %dec, %ContLoop ]
|
|
; CHECK: %[[SINKMUL:.*]] = mul i32 %N, %[[OP]]
|
|
; CHECK: %[[SINKSUB:.*]] = sub i32 %[[SINKMUL]], %N2
|
|
; CHECK: br label %Out12
|
|
;
|
|
; CHECK-LABEL:Out12.split.loop.exit1:
|
|
; CHECK: %[[OP2:.*]] = phi i32 [ %iv, %Loop ]
|
|
; CHECK: %[[SINKMUL2:.*]] = mul i32 %N, %[[OP2]]
|
|
; CHECK: %[[SINKSUB2:.*]] = sub i32 %[[SINKMUL2]], %N2
|
|
; CHECK: br label %Out12
|
|
;
|
|
; CHECK-LABEL:Out12:
|
|
; CHECK: %tmp1 = phi i32 [ %[[SINKSUB]], %Out12.split.loop.exit ], [ %[[SINKSUB2]], %Out12.split.loop.exit1 ]
|
|
; CHECK: %tmp2 = phi i32 [ %[[DEC]], %Out12.split.loop.exit ], [ %[[SINKSUB2]], %Out12.split.loop.exit1 ]
|
|
; CHECK: %add = add i32 %tmp1, %tmp2
|
|
define i32 @test18(i32 %N, i32 %N2) {
|
|
Entry:
|
|
br label %Loop
|
|
Loop:
|
|
%iv = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ]
|
|
%sink.mul = mul i32 %N, %iv
|
|
%sink.sub = sub i32 %sink.mul, %N2
|
|
%c0 = call i1 @getc()
|
|
br i1 %c0, label %ContLoop, label %Out12
|
|
ContLoop:
|
|
%dec = add i32 %iv, -1
|
|
%c1 = call i1 @getc()
|
|
br i1 %c1, label %Loop, label %Out12
|
|
Out12:
|
|
%tmp1 = phi i32 [%sink.sub, %ContLoop], [%sink.sub, %Loop]
|
|
%tmp2 = phi i32 [%dec, %ContLoop], [%sink.sub, %Loop]
|
|
%add = add i32 %tmp1, %tmp2
|
|
ret i32 %add
|
|
}
|
|
|
|
; Do not sink an instruction through a non-trivially replacable PHI, to avoid
|
|
; assert while splitting predecessors, if the terminator of predecessor is an
|
|
; indirectbr.
|
|
; CHECK-LABEL: @test19
|
|
; CHECK-LABEL: L0:
|
|
; CHECK: %sinkable = mul
|
|
; CHECK: %sinkable2 = add
|
|
|
|
define i32 @test19(i1 %cond, i1 %cond2, i8* %address, i32 %v1) nounwind {
|
|
entry:
|
|
br label %L0
|
|
L0:
|
|
%indirect.goto.dest = select i1 %cond, i8* blockaddress(@test19, %exit), i8* %address
|
|
%v2 = call i32 @getv()
|
|
%sinkable = mul i32 %v1, %v2
|
|
%sinkable2 = add i32 %v1, %v2
|
|
indirectbr i8* %indirect.goto.dest, [label %L1, label %exit]
|
|
|
|
L1:
|
|
%indirect.goto.dest2 = select i1 %cond2, i8* blockaddress(@test19, %exit), i8* %address
|
|
indirectbr i8* %indirect.goto.dest2, [label %L0, label %exit]
|
|
|
|
exit:
|
|
%r = phi i32 [%sinkable, %L0], [%sinkable2, %L1]
|
|
ret i32 %r
|
|
}
|
|
|
|
|
|
; Do not sink through a non-trivially replacable PHI if splitting predecessors
|
|
; not allowed in SplitBlockPredecessors().
|
|
;
|
|
; CHECK-LABEL: @test20
|
|
; CHECK-LABEL: while.cond
|
|
; CHECK: %sinkable = mul
|
|
; CHECK: %sinkable2 = add
|
|
define void @test20(i32* %s, i1 %b, i32 %v1, i32 %v2) personality i32 (...)* @__CxxFrameHandler3 {
|
|
entry:
|
|
br label %while.cond
|
|
while.cond:
|
|
%v = call i32 @getv()
|
|
%sinkable = mul i32 %v, %v2
|
|
%sinkable2 = add i32 %v, %v2
|
|
br i1 %b, label %try.cont, label %while.body
|
|
while.body:
|
|
invoke void @may_throw()
|
|
to label %while.body2 unwind label %catch.dispatch
|
|
while.body2:
|
|
invoke void @may_throw2()
|
|
to label %while.cond unwind label %catch.dispatch
|
|
catch.dispatch:
|
|
%.lcssa1 = phi i32 [ %sinkable, %while.body ], [ %sinkable2, %while.body2 ]
|
|
%cp = cleanuppad within none []
|
|
store i32 %.lcssa1, i32* %s
|
|
cleanupret from %cp unwind to caller
|
|
try.cont:
|
|
ret void
|
|
}
|
|
|
|
; The sinkable call should be sunk into an exit block split. After splitting
|
|
; the exit block, BlockColor for new blocks should be added properly so
|
|
; that we should be able to access valid ColorVector.
|
|
;
|
|
; CHECK-LABEL:@test21_pr36184
|
|
; CHECK-LABEL: Loop
|
|
; CHECK-NOT: %sinkableCall
|
|
; CHECK-LABEL:Out.split.loop.exit
|
|
; CHECK: %sinkableCall
|
|
define i32 @test21_pr36184(i8* %P) personality i32 (...)* @__CxxFrameHandler3 {
|
|
entry:
|
|
br label %loop.ph
|
|
|
|
loop.ph:
|
|
br label %Loop
|
|
|
|
Loop:
|
|
%sinkableCall = call i32 @strlen( i8* %P ) readonly
|
|
br i1 undef, label %ContLoop, label %Out
|
|
|
|
ContLoop:
|
|
br i1 undef, label %Loop, label %Out
|
|
|
|
Out:
|
|
%idx = phi i32 [ %sinkableCall, %Loop ], [0, %ContLoop ]
|
|
ret i32 %idx
|
|
}
|
|
|
|
; We do not support splitting a landingpad block if BlockColors is not empty.
|
|
; CHECK-LABEL: @test22
|
|
; CHECK-LABEL: while.body2
|
|
; CHECK-LABEL: %mul
|
|
; CHECK-NOT: lpadBB.split{{.*}}
|
|
define void @test22(i1 %b, i32 %v1, i32 %v2) personality i32 (...)* @__CxxFrameHandler3 {
|
|
entry:
|
|
br label %while.cond
|
|
while.cond:
|
|
br i1 %b, label %try.cont, label %while.body
|
|
|
|
while.body:
|
|
invoke void @may_throw()
|
|
to label %while.body2 unwind label %lpadBB
|
|
|
|
while.body2:
|
|
%v = call i32 @getv()
|
|
%mul = mul i32 %v, %v2
|
|
invoke void @may_throw2()
|
|
to label %while.cond unwind label %lpadBB
|
|
lpadBB:
|
|
%.lcssa1 = phi i32 [ 0, %while.body ], [ %mul, %while.body2 ]
|
|
landingpad { i8*, i32 }
|
|
catch i8* null
|
|
br label %lpadBBSucc1
|
|
|
|
lpadBBSucc1:
|
|
ret void
|
|
|
|
try.cont:
|
|
ret void
|
|
}
|
|
|
|
declare void @may_throw()
|
|
declare void @may_throw2()
|
|
declare i32 @__CxxFrameHandler3(...)
|
|
declare i32 @getv()
|
|
declare i1 @getc()
|
|
declare void @f(i32*)
|
|
declare void @g()
|