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llvm-project/llvm/test/MC/Mips/mips32r5
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Zlatko Buljan cba9f80ba8 [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 
Differential Revision: http://reviews.llvm.org/D18824

llvm-svn: 275050
 		2016-07-11 07:41:56 +00:00
..
abiflags.s
…
invalid-mips32.s [mips] Added support for the ERETNC instruction. 2015-07-20 12:28:56 +00:00
invalid-mips32r2.s [mips] Added support for the ERETNC instruction. 2015-07-20 12:28:56 +00:00
invalid-mips32r3.s [mips] Added support for the ERETNC instruction. 2015-07-20 12:28:56 +00:00
invalid-mips64r2.s
…
invalid.s [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
valid-xfail.s [mips][ias] Removed DSP/DSPr2 instructions from base architecture valid-xfail.s's. 2015-12-07 14:12:44 +00:00
valid.s [mips] Weaken asm predicate for memory offsets 2016-05-27 13:56:36 +00:00