forked from OSchip/llvm-project
532 lines
16 KiB
C++
532 lines
16 KiB
C++
//===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for X86.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "X86LegalizerInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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using namespace llvm;
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using namespace TargetOpcode;
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using namespace LegalizeActions;
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/// FIXME: The following static functions are SizeChangeStrategy functions
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/// that are meant to temporarily mimic the behaviour of the old legalization
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/// based on doubling/halving non-legal types as closely as possible. This is
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/// not entirly possible as only legalizing the types that are exactly a power
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/// of 2 times the size of the legal types would require specifying all those
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/// sizes explicitly.
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/// In practice, not specifying those isn't a problem, and the below functions
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/// should disappear quickly as we add support for legalizing non-power-of-2
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/// sized types further.
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static void
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addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
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const LegalizerInfo::SizeAndActionsVec &v) {
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for (unsigned i = 0; i < v.size(); ++i) {
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result.push_back(v[i]);
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if (i + 1 < v[i].first && i + 1 < v.size() &&
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v[i + 1].first != v[i].first + 1)
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result.push_back({v[i].first + 1, Unsupported});
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}
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}
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static LegalizerInfo::SizeAndActionsVec
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widen_1(const LegalizerInfo::SizeAndActionsVec &v) {
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assert(v.size() >= 1);
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assert(v[0].first > 1);
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LegalizerInfo::SizeAndActionsVec result = {{1, WidenScalar},
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{2, Unsupported}};
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addAndInterleaveWithUnsupported(result, v);
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auto Largest = result.back().first;
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result.push_back({Largest + 1, Unsupported});
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return result;
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}
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X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
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const X86TargetMachine &TM)
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: Subtarget(STI), TM(TM) {
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setLegalizerInfo32bit();
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setLegalizerInfo64bit();
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setLegalizerInfoSSE1();
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setLegalizerInfoSSE2();
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setLegalizerInfoSSE41();
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setLegalizerInfoAVX();
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setLegalizerInfoAVX2();
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setLegalizerInfoAVX512();
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setLegalizerInfoAVX512DQ();
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setLegalizerInfoAVX512BW();
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setLegalizeScalarToDifferentSizeStrategy(G_PHI, 0, widen_1);
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for (unsigned BinOp : {G_SUB, G_MUL, G_AND, G_OR, G_XOR})
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setLegalizeScalarToDifferentSizeStrategy(BinOp, 0, widen_1);
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for (unsigned MemOp : {G_LOAD, G_STORE})
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setLegalizeScalarToDifferentSizeStrategy(MemOp, 0,
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narrowToSmallerAndWidenToSmallest);
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setLegalizeScalarToDifferentSizeStrategy(
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G_GEP, 1, widenToLargerTypesUnsupportedOtherwise);
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setLegalizeScalarToDifferentSizeStrategy(
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G_CONSTANT, 0, widenToLargerTypesAndNarrowToLargest);
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computeTables();
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verify(*STI.getInstrInfo());
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}
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bool X86LegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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switch (MI.getIntrinsicID()) {
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case Intrinsic::memcpy:
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case Intrinsic::memset:
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case Intrinsic::memmove:
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if (createMemLibcall(MIRBuilder, MRI, MI) ==
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LegalizerHelper::UnableToLegalize)
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return false;
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MI.eraseFromParent();
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return true;
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default:
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break;
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}
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return true;
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}
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void X86LegalizerInfo::setLegalizerInfo32bit() {
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const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
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const LLT s1 = LLT::scalar(1);
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const LLT s8 = LLT::scalar(8);
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const LLT s16 = LLT::scalar(16);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT s128 = LLT::scalar(128);
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for (auto Ty : {p0, s1, s8, s16, s32})
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setAction({G_IMPLICIT_DEF, Ty}, Legal);
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for (auto Ty : {s8, s16, s32, p0})
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setAction({G_PHI, Ty}, Legal);
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for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
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for (auto Ty : {s8, s16, s32})
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setAction({BinOp, Ty}, Legal);
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for (unsigned Op : {G_UADDE}) {
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setAction({Op, s32}, Legal);
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setAction({Op, 1, s1}, Legal);
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}
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for (unsigned MemOp : {G_LOAD, G_STORE}) {
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for (auto Ty : {s8, s16, s32, p0})
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setAction({MemOp, Ty}, Legal);
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// And everything's fine in addrspace 0.
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setAction({MemOp, 1, p0}, Legal);
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}
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// Pointer-handling
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setAction({G_FRAME_INDEX, p0}, Legal);
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setAction({G_GLOBAL_VALUE, p0}, Legal);
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setAction({G_GEP, p0}, Legal);
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setAction({G_GEP, 1, s32}, Legal);
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if (!Subtarget.is64Bit()) {
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getActionDefinitionsBuilder(G_PTRTOINT)
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.legalForCartesianProduct({s1, s8, s16, s32}, {p0})
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.maxScalar(0, s32)
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.widenScalarToNextPow2(0, /*Min*/ 8);
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getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
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// Shifts and SDIV
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getActionDefinitionsBuilder(
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{G_SDIV, G_SREM, G_UDIV, G_UREM})
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.legalFor({s8, s16, s32})
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.clampScalar(0, s8, s32);
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getActionDefinitionsBuilder(
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{G_SHL, G_LSHR, G_ASHR})
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.legalFor({{s8, s8}, {s16, s8}, {s32, s8}})
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.clampScalar(0, s8, s32)
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.clampScalar(1, s8, s8);
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}
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// Control-flow
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setAction({G_BRCOND, s1}, Legal);
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// Constants
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for (auto Ty : {s8, s16, s32, p0})
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setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
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// Extensions
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for (auto Ty : {s8, s16, s32}) {
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setAction({G_ZEXT, Ty}, Legal);
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setAction({G_SEXT, Ty}, Legal);
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setAction({G_ANYEXT, Ty}, Legal);
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}
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setAction({G_ANYEXT, s128}, Legal);
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getActionDefinitionsBuilder(G_SEXT_INREG).lower();
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// Comparison
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setAction({G_ICMP, s1}, Legal);
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for (auto Ty : {s8, s16, s32, p0})
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setAction({G_ICMP, 1, Ty}, Legal);
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// Merge/Unmerge
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for (const auto &Ty : {s16, s32, s64}) {
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setAction({G_MERGE_VALUES, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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}
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for (const auto &Ty : {s8, s16, s32}) {
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setAction({G_MERGE_VALUES, 1, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, Ty}, Legal);
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}
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}
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void X86LegalizerInfo::setLegalizerInfo64bit() {
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if (!Subtarget.is64Bit())
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return;
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const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
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const LLT s1 = LLT::scalar(1);
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const LLT s8 = LLT::scalar(8);
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const LLT s16 = LLT::scalar(16);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT s128 = LLT::scalar(128);
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setAction({G_IMPLICIT_DEF, s64}, Legal);
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// Need to have that, as tryFoldImplicitDef will create this pattern:
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// s128 = EXTEND (G_IMPLICIT_DEF s32/s64) -> s128 = G_IMPLICIT_DEF
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setAction({G_IMPLICIT_DEF, s128}, Legal);
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setAction({G_PHI, s64}, Legal);
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for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
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setAction({BinOp, s64}, Legal);
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for (unsigned MemOp : {G_LOAD, G_STORE})
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setAction({MemOp, s64}, Legal);
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// Pointer-handling
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setAction({G_GEP, 1, s64}, Legal);
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getActionDefinitionsBuilder(G_PTRTOINT)
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.legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
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.maxScalar(0, s64)
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.widenScalarToNextPow2(0, /*Min*/ 8);
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getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s64}});
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// Constants
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setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
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// Extensions
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for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
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setAction({extOp, s64}, Legal);
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}
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getActionDefinitionsBuilder(G_SITOFP)
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.legalForCartesianProduct({s32, s64})
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.clampScalar(1, s32, s64)
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.widenScalarToNextPow2(1)
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.clampScalar(0, s32, s64)
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.widenScalarToNextPow2(0);
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getActionDefinitionsBuilder(G_FPTOSI)
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.legalForCartesianProduct({s32, s64})
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.clampScalar(1, s32, s64)
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.widenScalarToNextPow2(0)
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.clampScalar(0, s32, s64)
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.widenScalarToNextPow2(1);
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// Comparison
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setAction({G_ICMP, 1, s64}, Legal);
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getActionDefinitionsBuilder(G_FCMP)
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.legalForCartesianProduct({s8}, {s32, s64})
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.clampScalar(0, s8, s8)
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.clampScalar(1, s32, s64)
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.widenScalarToNextPow2(1);
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// Divisions
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getActionDefinitionsBuilder(
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{G_SDIV, G_SREM, G_UDIV, G_UREM})
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.legalFor({s8, s16, s32, s64})
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.clampScalar(0, s8, s64);
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// Shifts
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getActionDefinitionsBuilder(
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{G_SHL, G_LSHR, G_ASHR})
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.legalFor({{s8, s8}, {s16, s8}, {s32, s8}, {s64, s8}})
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.clampScalar(0, s8, s64)
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.clampScalar(1, s8, s8);
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// Merge/Unmerge
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setAction({G_MERGE_VALUES, s128}, Legal);
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setAction({G_UNMERGE_VALUES, 1, s128}, Legal);
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setAction({G_MERGE_VALUES, 1, s128}, Legal);
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setAction({G_UNMERGE_VALUES, s128}, Legal);
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}
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void X86LegalizerInfo::setLegalizerInfoSSE1() {
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if (!Subtarget.hasSSE1())
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return;
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v2s64 = LLT::vector(2, 64);
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for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
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for (auto Ty : {s32, v4s32})
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setAction({BinOp, Ty}, Legal);
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for (unsigned MemOp : {G_LOAD, G_STORE})
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for (auto Ty : {v4s32, v2s64})
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setAction({MemOp, Ty}, Legal);
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// Constants
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setAction({TargetOpcode::G_FCONSTANT, s32}, Legal);
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// Merge/Unmerge
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for (const auto &Ty : {v4s32, v2s64}) {
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setAction({G_CONCAT_VECTORS, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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}
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setAction({G_MERGE_VALUES, 1, s64}, Legal);
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setAction({G_UNMERGE_VALUES, s64}, Legal);
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}
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void X86LegalizerInfo::setLegalizerInfoSSE2() {
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if (!Subtarget.hasSSE2())
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return;
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT v16s8 = LLT::vector(16, 8);
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const LLT v8s16 = LLT::vector(8, 16);
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT v32s8 = LLT::vector(32, 8);
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const LLT v16s16 = LLT::vector(16, 16);
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const LLT v8s32 = LLT::vector(8, 32);
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const LLT v4s64 = LLT::vector(4, 64);
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for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
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for (auto Ty : {s64, v2s64})
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setAction({BinOp, Ty}, Legal);
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for (unsigned BinOp : {G_ADD, G_SUB})
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for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
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setAction({BinOp, Ty}, Legal);
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setAction({G_MUL, v8s16}, Legal);
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setAction({G_FPEXT, s64}, Legal);
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setAction({G_FPEXT, 1, s32}, Legal);
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setAction({G_FPTRUNC, s32}, Legal);
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setAction({G_FPTRUNC, 1, s64}, Legal);
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// Constants
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setAction({TargetOpcode::G_FCONSTANT, s64}, Legal);
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// Merge/Unmerge
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for (const auto &Ty :
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{v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
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setAction({G_CONCAT_VECTORS, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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}
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for (const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) {
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setAction({G_CONCAT_VECTORS, 1, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, Ty}, Legal);
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}
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}
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void X86LegalizerInfo::setLegalizerInfoSSE41() {
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if (!Subtarget.hasSSE41())
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return;
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const LLT v4s32 = LLT::vector(4, 32);
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setAction({G_MUL, v4s32}, Legal);
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}
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void X86LegalizerInfo::setLegalizerInfoAVX() {
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if (!Subtarget.hasAVX())
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return;
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const LLT v16s8 = LLT::vector(16, 8);
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const LLT v8s16 = LLT::vector(8, 16);
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT v32s8 = LLT::vector(32, 8);
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const LLT v64s8 = LLT::vector(64, 8);
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const LLT v16s16 = LLT::vector(16, 16);
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const LLT v32s16 = LLT::vector(32, 16);
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const LLT v8s32 = LLT::vector(8, 32);
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const LLT v16s32 = LLT::vector(16, 32);
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const LLT v4s64 = LLT::vector(4, 64);
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const LLT v8s64 = LLT::vector(8, 64);
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for (unsigned MemOp : {G_LOAD, G_STORE})
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for (auto Ty : {v8s32, v4s64})
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setAction({MemOp, Ty}, Legal);
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for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) {
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setAction({G_INSERT, Ty}, Legal);
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setAction({G_EXTRACT, 1, Ty}, Legal);
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}
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for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) {
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setAction({G_INSERT, 1, Ty}, Legal);
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setAction({G_EXTRACT, Ty}, Legal);
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}
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// Merge/Unmerge
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for (const auto &Ty :
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{v32s8, v64s8, v16s16, v32s16, v8s32, v16s32, v4s64, v8s64}) {
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setAction({G_CONCAT_VECTORS, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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}
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for (const auto &Ty :
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{v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
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setAction({G_CONCAT_VECTORS, 1, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, Ty}, Legal);
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}
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}
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void X86LegalizerInfo::setLegalizerInfoAVX2() {
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if (!Subtarget.hasAVX2())
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return;
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const LLT v32s8 = LLT::vector(32, 8);
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const LLT v16s16 = LLT::vector(16, 16);
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const LLT v8s32 = LLT::vector(8, 32);
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const LLT v4s64 = LLT::vector(4, 64);
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const LLT v64s8 = LLT::vector(64, 8);
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const LLT v32s16 = LLT::vector(32, 16);
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const LLT v16s32 = LLT::vector(16, 32);
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const LLT v8s64 = LLT::vector(8, 64);
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for (unsigned BinOp : {G_ADD, G_SUB})
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for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
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setAction({BinOp, Ty}, Legal);
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for (auto Ty : {v16s16, v8s32})
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setAction({G_MUL, Ty}, Legal);
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// Merge/Unmerge
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for (const auto &Ty : {v64s8, v32s16, v16s32, v8s64}) {
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setAction({G_CONCAT_VECTORS, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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}
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for (const auto &Ty : {v32s8, v16s16, v8s32, v4s64}) {
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setAction({G_CONCAT_VECTORS, 1, Ty}, Legal);
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setAction({G_UNMERGE_VALUES, Ty}, Legal);
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}
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}
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void X86LegalizerInfo::setLegalizerInfoAVX512() {
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if (!Subtarget.hasAVX512())
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return;
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const LLT v16s8 = LLT::vector(16, 8);
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const LLT v8s16 = LLT::vector(8, 16);
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT v32s8 = LLT::vector(32, 8);
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const LLT v16s16 = LLT::vector(16, 16);
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const LLT v8s32 = LLT::vector(8, 32);
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const LLT v4s64 = LLT::vector(4, 64);
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const LLT v64s8 = LLT::vector(64, 8);
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const LLT v32s16 = LLT::vector(32, 16);
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const LLT v16s32 = LLT::vector(16, 32);
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const LLT v8s64 = LLT::vector(8, 64);
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for (unsigned BinOp : {G_ADD, G_SUB})
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for (auto Ty : {v16s32, v8s64})
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setAction({BinOp, Ty}, Legal);
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setAction({G_MUL, v16s32}, Legal);
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for (unsigned MemOp : {G_LOAD, G_STORE})
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for (auto Ty : {v16s32, v8s64})
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setAction({MemOp, Ty}, Legal);
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for (auto Ty : {v64s8, v32s16, v16s32, v8s64}) {
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setAction({G_INSERT, Ty}, Legal);
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setAction({G_EXTRACT, 1, Ty}, Legal);
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}
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for (auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64}) {
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setAction({G_INSERT, 1, Ty}, Legal);
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setAction({G_EXTRACT, Ty}, Legal);
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}
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/************ VLX *******************/
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if (!Subtarget.hasVLX())
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return;
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for (auto Ty : {v4s32, v8s32})
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setAction({G_MUL, Ty}, Legal);
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}
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void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
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if (!(Subtarget.hasAVX512() && Subtarget.hasDQI()))
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return;
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|
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const LLT v8s64 = LLT::vector(8, 64);
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setAction({G_MUL, v8s64}, Legal);
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|
|
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/************ VLX *******************/
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if (!Subtarget.hasVLX())
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return;
|
|
|
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT v4s64 = LLT::vector(4, 64);
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|
|
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for (auto Ty : {v2s64, v4s64})
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|
setAction({G_MUL, Ty}, Legal);
|
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}
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|
|
|
void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
|
|
if (!(Subtarget.hasAVX512() && Subtarget.hasBWI()))
|
|
return;
|
|
|
|
const LLT v64s8 = LLT::vector(64, 8);
|
|
const LLT v32s16 = LLT::vector(32, 16);
|
|
|
|
for (unsigned BinOp : {G_ADD, G_SUB})
|
|
for (auto Ty : {v64s8, v32s16})
|
|
setAction({BinOp, Ty}, Legal);
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|
|
|
setAction({G_MUL, v32s16}, Legal);
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|
|
|
/************ VLX *******************/
|
|
if (!Subtarget.hasVLX())
|
|
return;
|
|
|
|
const LLT v8s16 = LLT::vector(8, 16);
|
|
const LLT v16s16 = LLT::vector(16, 16);
|
|
|
|
for (auto Ty : {v8s16, v16s16})
|
|
setAction({G_MUL, Ty}, Legal);
|
|
}
|