forked from OSchip/llvm-project
1431 lines
78 KiB
TableGen
1431 lines
78 KiB
TableGen
//=- AArch64SVEInstrInfo.td - AArch64 SVE Instructions -*- tablegen -*-----=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 Scalable Vector Extension (SVE) Instruction definitions.
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//
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//===----------------------------------------------------------------------===//
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let Predicates = [HasSVE] in {
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def RDFFR_PPz : sve_int_rdffr_pred<0b0, "rdffr">;
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def RDFFRS_PPz : sve_int_rdffr_pred<0b1, "rdffrs">;
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def RDFFR_P : sve_int_rdffr_unpred<"rdffr">;
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def SETFFR : sve_int_setffr<"setffr">;
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def WRFFR : sve_int_wrffr<"wrffr">;
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defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">;
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defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">;
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defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd">;
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defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd">;
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defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">;
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defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">;
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defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
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defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
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defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
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defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
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defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">;
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defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">;
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defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr">;
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defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">;
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defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">;
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defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">;
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defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic">;
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defm ADD_ZI : sve_int_arith_imm0<0b000, "add">;
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defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">;
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defm SUBR_ZI : sve_int_arith_imm0<0b011, "subr">;
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defm SQADD_ZI : sve_int_arith_imm0<0b100, "sqadd">;
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defm UQADD_ZI : sve_int_arith_imm0<0b101, "uqadd">;
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defm SQSUB_ZI : sve_int_arith_imm0<0b110, "sqsub">;
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defm UQSUB_ZI : sve_int_arith_imm0<0b111, "uqsub">;
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defm MAD_ZPmZZ : sve_int_mladdsub_vvv_pred<0b0, "mad">;
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defm MSB_ZPmZZ : sve_int_mladdsub_vvv_pred<0b1, "msb">;
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defm MLA_ZPmZZ : sve_int_mlas_vvv_pred<0b0, "mla">;
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defm MLS_ZPmZZ : sve_int_mlas_vvv_pred<0b1, "mls">;
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// SVE predicated integer reductions.
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defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv">;
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defm UADDV_VPZ : sve_int_reduce_0_uaddv<0b001, "uaddv">;
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defm SMAXV_VPZ : sve_int_reduce_1<0b000, "smaxv">;
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defm UMAXV_VPZ : sve_int_reduce_1<0b001, "umaxv">;
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defm SMINV_VPZ : sve_int_reduce_1<0b010, "sminv">;
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defm UMINV_VPZ : sve_int_reduce_1<0b011, "uminv">;
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defm ORV_VPZ : sve_int_reduce_2<0b000, "orv">;
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defm EORV_VPZ : sve_int_reduce_2<0b001, "eorv">;
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defm ANDV_VPZ : sve_int_reduce_2<0b010, "andv">;
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defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">;
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defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">;
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defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">;
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defm SMAX_ZI : sve_int_arith_imm1<0b00, "smax", simm8>;
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defm SMIN_ZI : sve_int_arith_imm1<0b10, "smin", simm8>;
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defm UMAX_ZI : sve_int_arith_imm1<0b01, "umax", imm0_255>;
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defm UMIN_ZI : sve_int_arith_imm1<0b11, "umin", imm0_255>;
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defm MUL_ZI : sve_int_arith_imm2<"mul">;
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defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul">;
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defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh">;
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defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh">;
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defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv">;
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defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv">;
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defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr">;
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defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr">;
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defm SDOT_ZZZ : sve_intx_dot<0b0, "sdot">;
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defm UDOT_ZZZ : sve_intx_dot<0b1, "udot">;
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defm SDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b0, "sdot">;
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defm UDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b1, "udot">;
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defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb">;
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defm UXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b001, "uxtb">;
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defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth">;
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defm UXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b011, "uxth">;
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defm SXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b100, "sxtw">;
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defm UXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b101, "uxtw">;
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defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs">;
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defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg">;
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defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls">;
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defm CLZ_ZPmZ : sve_int_un_pred_arit_1< 0b001, "clz">;
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defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt">;
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defm CNOT_ZPmZ : sve_int_un_pred_arit_1< 0b011, "cnot">;
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defm NOT_ZPmZ : sve_int_un_pred_arit_1< 0b110, "not">;
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defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs">;
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defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg">;
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defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax">;
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defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax">;
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defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin">;
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defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin">;
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defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd">;
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defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd">;
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defm FRECPE_ZZ : sve_fp_2op_u_zd<0b110, "frecpe">;
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defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte">;
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defm FADD_ZPmI : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>;
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defm FSUB_ZPmI : sve_fp_2op_i_p_zds<0b001, "fsub", sve_fpimm_half_one>;
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defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
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defm FSUBR_ZPmI : sve_fp_2op_i_p_zds<0b011, "fsubr", sve_fpimm_half_one>;
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defm FMAXNM_ZPmI : sve_fp_2op_i_p_zds<0b100, "fmaxnm", sve_fpimm_zero_one>;
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defm FMINNM_ZPmI : sve_fp_2op_i_p_zds<0b101, "fminnm", sve_fpimm_zero_one>;
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defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>;
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defm FMIN_ZPmI : sve_fp_2op_i_p_zds<0b111, "fmin", sve_fpimm_zero_one>;
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defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd">;
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defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub">;
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defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul">;
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defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr">;
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defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm">;
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defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm">;
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defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax">;
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defm FMIN_ZPmZ : sve_fp_2op_p_zds<0b0111, "fmin">;
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defm FABD_ZPmZ : sve_fp_2op_p_zds<0b1000, "fabd">;
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defm FSCALE_ZPmZ : sve_fp_2op_p_zds<0b1001, "fscale">;
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defm FMULX_ZPmZ : sve_fp_2op_p_zds<0b1010, "fmulx">;
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defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr">;
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defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv">;
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defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd">;
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defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub">;
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defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul">;
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defm FTSMUL_ZZZ : sve_fp_3op_u_zd<0b011, "ftsmul">;
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defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps">;
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defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts">;
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defm FTSSEL_ZZZ : sve_int_bin_cons_misc_0_b<"ftssel">;
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defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">;
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defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">;
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defm FMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b00, "fmla">;
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defm FMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b01, "fmls">;
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defm FNMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b10, "fnmla">;
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defm FNMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b11, "fnmls">;
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defm FMAD_ZPmZZ : sve_fp_3op_p_zds_b<0b00, "fmad">;
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defm FMSB_ZPmZZ : sve_fp_3op_p_zds_b<0b01, "fmsb">;
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defm FNMAD_ZPmZZ : sve_fp_3op_p_zds_b<0b10, "fnmad">;
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defm FNMSB_ZPmZZ : sve_fp_3op_p_zds_b<0b11, "fnmsb">;
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defm FTMAD_ZZI : sve_fp_ftmad<"ftmad">;
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defm FMLA_ZZZI : sve_fp_fma_by_indexed_elem<0b0, "fmla">;
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defm FMLS_ZZZI : sve_fp_fma_by_indexed_elem<0b1, "fmls">;
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defm FCMLA_ZZZI : sve_fp_fcmla_by_indexed_elem<"fcmla">;
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defm FMUL_ZZZI : sve_fp_fmul_by_indexed_elem<"fmul">;
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// SVE floating point reductions.
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defm FADDA_VPZ : sve_fp_2op_p_vd<0b000, "fadda">;
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defm FADDV_VPZ : sve_fp_fast_red<0b000, "faddv">;
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defm FMAXNMV_VPZ : sve_fp_fast_red<0b100, "fmaxnmv">;
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defm FMINNMV_VPZ : sve_fp_fast_red<0b101, "fminnmv">;
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defm FMAXV_VPZ : sve_fp_fast_red<0b110, "fmaxv">;
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defm FMINV_VPZ : sve_fp_fast_red<0b111, "fminv">;
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// Splat immediate (unpredicated)
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defm DUP_ZI : sve_int_dup_imm<"dup">;
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defm FDUP_ZI : sve_int_dup_fpimm<"fdup">;
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defm DUPM_ZI : sve_int_dup_mask_imm<"dupm">;
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// Splat immediate (predicated)
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defm CPY_ZPmI : sve_int_dup_imm_pred_merge<"cpy">;
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defm CPY_ZPzI : sve_int_dup_imm_pred_zero<"cpy">;
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defm FCPY_ZPmI : sve_int_dup_fpimm_pred<"fcpy">;
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// Splat scalar register (unpredicated, GPR or vector + element index)
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defm DUP_ZR : sve_int_perm_dup_r<"dup">;
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defm DUP_ZZI : sve_int_perm_dup_i<"dup">;
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// Splat scalar register (predicated)
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defm CPY_ZPmR : sve_int_perm_cpy_r<"cpy">;
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defm CPY_ZPmV : sve_int_perm_cpy_v<"cpy">;
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// Select elements from either vector (predicated)
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defm SEL_ZPZZ : sve_int_sel_vvv<"sel">;
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defm SPLICE_ZPZ : sve_int_perm_splice<"splice">;
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defm COMPACT_ZPZ : sve_int_perm_compact<"compact">;
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defm INSR_ZR : sve_int_perm_insrs<"insr">;
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defm INSR_ZV : sve_int_perm_insrv<"insr">;
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def EXT_ZZI : sve_int_perm_extract_i<"ext">;
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defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit">;
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defm REVB_ZPmZ : sve_int_perm_rev_revb<"revb">;
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defm REVH_ZPmZ : sve_int_perm_rev_revh<"revh">;
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defm REVW_ZPmZ : sve_int_perm_rev_revw<"revw">;
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defm REV_PP : sve_int_perm_reverse_p<"rev">;
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defm REV_ZZ : sve_int_perm_reverse_z<"rev">;
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defm SUNPKLO_ZZ : sve_int_perm_unpk<0b00, "sunpklo">;
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defm SUNPKHI_ZZ : sve_int_perm_unpk<0b01, "sunpkhi">;
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defm UUNPKLO_ZZ : sve_int_perm_unpk<0b10, "uunpklo">;
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defm UUNPKHI_ZZ : sve_int_perm_unpk<0b11, "uunpkhi">;
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def PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo">;
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def PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi">;
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defm MOVPRFX_ZPzZ : sve_int_movprfx_pred_zero<0b000, "movprfx">;
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defm MOVPRFX_ZPmZ : sve_int_movprfx_pred_merge<0b001, "movprfx">;
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def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>;
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def FEXPA_ZZ_H : sve_int_bin_cons_misc_0_c<0b01000000, "fexpa", ZPR16>;
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def FEXPA_ZZ_S : sve_int_bin_cons_misc_0_c<0b10000000, "fexpa", ZPR32>;
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def FEXPA_ZZ_D : sve_int_bin_cons_misc_0_c<0b11000000, "fexpa", ZPR64>;
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def BRKPA_PPzPP : sve_int_brkp<0b00, "brkpa">;
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def BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas">;
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def BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb">;
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def BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs">;
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def BRKN_PPzP : sve_int_brkn<0b0, "brkn">;
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def BRKNS_PPzP : sve_int_brkn<0b1, "brkns">;
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defm BRKA_PPzP : sve_int_break_z<0b000, "brka">;
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defm BRKA_PPmP : sve_int_break_m<0b001, "brka">;
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defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas">;
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defm BRKB_PPzP : sve_int_break_z<0b100, "brkb">;
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defm BRKB_PPmP : sve_int_break_m<0b101, "brkb">;
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defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs">;
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def PTEST_PP : sve_int_ptest<0b010000, "ptest">;
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def PFALSE : sve_int_pfalse<0b000000, "pfalse">;
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defm PFIRST : sve_int_pfirst<0b00000, "pfirst">;
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defm PNEXT : sve_int_pnext<0b00110, "pnext">;
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def AND_PPzPP : sve_int_pred_log<0b0000, "and">;
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def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">;
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def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">;
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def SEL_PPPP : sve_int_pred_log<0b0011, "sel">;
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def ANDS_PPzPP : sve_int_pred_log<0b0100, "ands">;
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def BICS_PPzPP : sve_int_pred_log<0b0101, "bics">;
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def EORS_PPzPP : sve_int_pred_log<0b0110, "eors">;
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def ORR_PPzPP : sve_int_pred_log<0b1000, "orr">;
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def ORN_PPzPP : sve_int_pred_log<0b1001, "orn">;
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def NOR_PPzPP : sve_int_pred_log<0b1010, "nor">;
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def NAND_PPzPP : sve_int_pred_log<0b1011, "nand">;
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def ORRS_PPzPP : sve_int_pred_log<0b1100, "orrs">;
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def ORNS_PPzPP : sve_int_pred_log<0b1101, "orns">;
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def NORS_PPzPP : sve_int_pred_log<0b1110, "nors">;
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def NANDS_PPzPP : sve_int_pred_log<0b1111, "nands">;
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defm CLASTA_RPZ : sve_int_perm_clast_rz<0, "clasta">;
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defm CLASTB_RPZ : sve_int_perm_clast_rz<1, "clastb">;
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defm CLASTA_VPZ : sve_int_perm_clast_vz<0, "clasta">;
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defm CLASTB_VPZ : sve_int_perm_clast_vz<1, "clastb">;
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defm CLASTA_ZPZ : sve_int_perm_clast_zz<0, "clasta">;
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defm CLASTB_ZPZ : sve_int_perm_clast_zz<1, "clastb">;
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defm LASTA_RPZ : sve_int_perm_last_r<0, "lasta">;
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defm LASTB_RPZ : sve_int_perm_last_r<1, "lastb">;
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defm LASTA_VPZ : sve_int_perm_last_v<0, "lasta">;
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defm LASTB_VPZ : sve_int_perm_last_v<1, "lastb">;
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// continuous load with reg+immediate
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defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>;
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defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;
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defm LD1B_S_IMM : sve_mem_cld_si<0b0010, "ld1b", Z_s, ZPR32>;
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defm LD1B_D_IMM : sve_mem_cld_si<0b0011, "ld1b", Z_d, ZPR64>;
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defm LD1SW_D_IMM : sve_mem_cld_si<0b0100, "ld1sw", Z_d, ZPR64>;
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defm LD1H_IMM : sve_mem_cld_si<0b0101, "ld1h", Z_h, ZPR16>;
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defm LD1H_S_IMM : sve_mem_cld_si<0b0110, "ld1h", Z_s, ZPR32>;
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defm LD1H_D_IMM : sve_mem_cld_si<0b0111, "ld1h", Z_d, ZPR64>;
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defm LD1SH_D_IMM : sve_mem_cld_si<0b1000, "ld1sh", Z_d, ZPR64>;
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defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
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defm LD1W_IMM : sve_mem_cld_si<0b1010, "ld1w", Z_s, ZPR32>;
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defm LD1W_D_IMM : sve_mem_cld_si<0b1011, "ld1w", Z_d, ZPR64>;
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defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
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defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;
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defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>;
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defm LD1D_IMM : sve_mem_cld_si<0b1111, "ld1d", Z_d, ZPR64>;
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// LD1R loads (splat scalar to vector)
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defm LD1RB_IMM : sve_mem_ld_dup<0b00, 0b00, "ld1rb", Z_b, ZPR8, uimm6s1>;
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defm LD1RB_H_IMM : sve_mem_ld_dup<0b00, 0b01, "ld1rb", Z_h, ZPR16, uimm6s1>;
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defm LD1RB_S_IMM : sve_mem_ld_dup<0b00, 0b10, "ld1rb", Z_s, ZPR32, uimm6s1>;
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defm LD1RB_D_IMM : sve_mem_ld_dup<0b00, 0b11, "ld1rb", Z_d, ZPR64, uimm6s1>;
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defm LD1RSW_IMM : sve_mem_ld_dup<0b01, 0b00, "ld1rsw", Z_d, ZPR64, uimm6s4>;
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defm LD1RH_IMM : sve_mem_ld_dup<0b01, 0b01, "ld1rh", Z_h, ZPR16, uimm6s2>;
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defm LD1RH_S_IMM : sve_mem_ld_dup<0b01, 0b10, "ld1rh", Z_s, ZPR32, uimm6s2>;
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defm LD1RH_D_IMM : sve_mem_ld_dup<0b01, 0b11, "ld1rh", Z_d, ZPR64, uimm6s2>;
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defm LD1RSH_D_IMM : sve_mem_ld_dup<0b10, 0b00, "ld1rsh", Z_d, ZPR64, uimm6s2>;
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defm LD1RSH_S_IMM : sve_mem_ld_dup<0b10, 0b01, "ld1rsh", Z_s, ZPR32, uimm6s2>;
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defm LD1RW_IMM : sve_mem_ld_dup<0b10, 0b10, "ld1rw", Z_s, ZPR32, uimm6s4>;
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defm LD1RW_D_IMM : sve_mem_ld_dup<0b10, 0b11, "ld1rw", Z_d, ZPR64, uimm6s4>;
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defm LD1RSB_D_IMM : sve_mem_ld_dup<0b11, 0b00, "ld1rsb", Z_d, ZPR64, uimm6s1>;
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defm LD1RSB_S_IMM : sve_mem_ld_dup<0b11, 0b01, "ld1rsb", Z_s, ZPR32, uimm6s1>;
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defm LD1RSB_H_IMM : sve_mem_ld_dup<0b11, 0b10, "ld1rsb", Z_h, ZPR16, uimm6s1>;
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defm LD1RD_IMM : sve_mem_ld_dup<0b11, 0b11, "ld1rd", Z_d, ZPR64, uimm6s8>;
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// LD1RQ loads (load quadword-vector and splat to scalable vector)
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defm LD1RQ_B_IMM : sve_mem_ldqr_si<0b00, "ld1rqb", Z_b, ZPR8>;
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defm LD1RQ_H_IMM : sve_mem_ldqr_si<0b01, "ld1rqh", Z_h, ZPR16>;
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defm LD1RQ_W_IMM : sve_mem_ldqr_si<0b10, "ld1rqw", Z_s, ZPR32>;
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defm LD1RQ_D_IMM : sve_mem_ldqr_si<0b11, "ld1rqd", Z_d, ZPR64>;
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defm LD1RQ_B : sve_mem_ldqr_ss<0b00, "ld1rqb", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm LD1RQ_H : sve_mem_ldqr_ss<0b01, "ld1rqh", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm LD1RQ_W : sve_mem_ldqr_ss<0b10, "ld1rqw", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm LD1RQ_D : sve_mem_ldqr_ss<0b11, "ld1rqd", Z_d, ZPR64, GPR64NoXZRshifted64>;
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// continuous load with reg+reg addressing.
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defm LD1B : sve_mem_cld_ss<0b0000, "ld1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
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defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64NoXZRshifted8>;
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defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64NoXZRshifted8>;
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defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>;
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defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64NoXZRshifted16>;
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defm LD1H_D : sve_mem_cld_ss<0b0111, "ld1h", Z_d, ZPR64, GPR64NoXZRshifted16>;
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defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64NoXZRshifted16>;
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defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>;
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defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
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defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>;
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defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>;
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defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>;
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defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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// non-faulting continuous load with reg+immediate
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defm LDNF1B_IMM : sve_mem_cldnf_si<0b0000, "ldnf1b", Z_b, ZPR8>;
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defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>;
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defm LDNF1B_S_IMM : sve_mem_cldnf_si<0b0010, "ldnf1b", Z_s, ZPR32>;
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defm LDNF1B_D_IMM : sve_mem_cldnf_si<0b0011, "ldnf1b", Z_d, ZPR64>;
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defm LDNF1SW_D_IMM : sve_mem_cldnf_si<0b0100, "ldnf1sw", Z_d, ZPR64>;
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defm LDNF1H_IMM : sve_mem_cldnf_si<0b0101, "ldnf1h", Z_h, ZPR16>;
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defm LDNF1H_S_IMM : sve_mem_cldnf_si<0b0110, "ldnf1h", Z_s, ZPR32>;
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defm LDNF1H_D_IMM : sve_mem_cldnf_si<0b0111, "ldnf1h", Z_d, ZPR64>;
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defm LDNF1SH_D_IMM : sve_mem_cldnf_si<0b1000, "ldnf1sh", Z_d, ZPR64>;
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defm LDNF1SH_S_IMM : sve_mem_cldnf_si<0b1001, "ldnf1sh", Z_s, ZPR32>;
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defm LDNF1W_IMM : sve_mem_cldnf_si<0b1010, "ldnf1w", Z_s, ZPR32>;
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defm LDNF1W_D_IMM : sve_mem_cldnf_si<0b1011, "ldnf1w", Z_d, ZPR64>;
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defm LDNF1SB_D_IMM : sve_mem_cldnf_si<0b1100, "ldnf1sb", Z_d, ZPR64>;
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defm LDNF1SB_S_IMM : sve_mem_cldnf_si<0b1101, "ldnf1sb", Z_s, ZPR32>;
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defm LDNF1SB_H_IMM : sve_mem_cldnf_si<0b1110, "ldnf1sb", Z_h, ZPR16>;
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defm LDNF1D_IMM : sve_mem_cldnf_si<0b1111, "ldnf1d", Z_d, ZPR64>;
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// First-faulting loads with reg+reg addressing.
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defm LDFF1B : sve_mem_cldff_ss<0b0000, "ldff1b", Z_b, ZPR8, GPR64shifted8>;
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defm LDFF1B_H : sve_mem_cldff_ss<0b0001, "ldff1b", Z_h, ZPR16, GPR64shifted8>;
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defm LDFF1B_S : sve_mem_cldff_ss<0b0010, "ldff1b", Z_s, ZPR32, GPR64shifted8>;
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defm LDFF1B_D : sve_mem_cldff_ss<0b0011, "ldff1b", Z_d, ZPR64, GPR64shifted8>;
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defm LDFF1SW_D : sve_mem_cldff_ss<0b0100, "ldff1sw", Z_d, ZPR64, GPR64shifted32>;
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defm LDFF1H : sve_mem_cldff_ss<0b0101, "ldff1h", Z_h, ZPR16, GPR64shifted16>;
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defm LDFF1H_S : sve_mem_cldff_ss<0b0110, "ldff1h", Z_s, ZPR32, GPR64shifted16>;
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defm LDFF1H_D : sve_mem_cldff_ss<0b0111, "ldff1h", Z_d, ZPR64, GPR64shifted16>;
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defm LDFF1SH_D : sve_mem_cldff_ss<0b1000, "ldff1sh", Z_d, ZPR64, GPR64shifted16>;
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defm LDFF1SH_S : sve_mem_cldff_ss<0b1001, "ldff1sh", Z_s, ZPR32, GPR64shifted16>;
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defm LDFF1W : sve_mem_cldff_ss<0b1010, "ldff1w", Z_s, ZPR32, GPR64shifted32>;
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defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>;
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defm LDFF1SB_D : sve_mem_cldff_ss<0b1100, "ldff1sb", Z_d, ZPR64, GPR64shifted8>;
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defm LDFF1SB_S : sve_mem_cldff_ss<0b1101, "ldff1sb", Z_s, ZPR32, GPR64shifted8>;
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defm LDFF1SB_H : sve_mem_cldff_ss<0b1110, "ldff1sb", Z_h, ZPR16, GPR64shifted8>;
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defm LDFF1D : sve_mem_cldff_ss<0b1111, "ldff1d", Z_d, ZPR64, GPR64shifted64>;
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// LD(2|3|4) structured loads with reg+immediate
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defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, ZZ_b, "ld2b", simm4s2>;
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defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, ZZZ_b, "ld3b", simm4s3>;
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defm LD4B_IMM : sve_mem_eld_si<0b00, 0b11, ZZZZ_b, "ld4b", simm4s4>;
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defm LD2H_IMM : sve_mem_eld_si<0b01, 0b01, ZZ_h, "ld2h", simm4s2>;
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defm LD3H_IMM : sve_mem_eld_si<0b01, 0b10, ZZZ_h, "ld3h", simm4s3>;
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defm LD4H_IMM : sve_mem_eld_si<0b01, 0b11, ZZZZ_h, "ld4h", simm4s4>;
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defm LD2W_IMM : sve_mem_eld_si<0b10, 0b01, ZZ_s, "ld2w", simm4s2>;
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defm LD3W_IMM : sve_mem_eld_si<0b10, 0b10, ZZZ_s, "ld3w", simm4s3>;
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defm LD4W_IMM : sve_mem_eld_si<0b10, 0b11, ZZZZ_s, "ld4w", simm4s4>;
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defm LD2D_IMM : sve_mem_eld_si<0b11, 0b01, ZZ_d, "ld2d", simm4s2>;
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defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d, "ld3d", simm4s3>;
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defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4s4>;
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// LD(2|3|4) structured loads (register + register)
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def LD2B : sve_mem_eld_ss<0b00, 0b01, ZZ_b, "ld2b", GPR64NoXZRshifted8>;
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def LD3B : sve_mem_eld_ss<0b00, 0b10, ZZZ_b, "ld3b", GPR64NoXZRshifted8>;
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def LD4B : sve_mem_eld_ss<0b00, 0b11, ZZZZ_b, "ld4b", GPR64NoXZRshifted8>;
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def LD2H : sve_mem_eld_ss<0b01, 0b01, ZZ_h, "ld2h", GPR64NoXZRshifted16>;
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def LD3H : sve_mem_eld_ss<0b01, 0b10, ZZZ_h, "ld3h", GPR64NoXZRshifted16>;
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def LD4H : sve_mem_eld_ss<0b01, 0b11, ZZZZ_h, "ld4h", GPR64NoXZRshifted16>;
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def LD2W : sve_mem_eld_ss<0b10, 0b01, ZZ_s, "ld2w", GPR64NoXZRshifted32>;
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def LD3W : sve_mem_eld_ss<0b10, 0b10, ZZZ_s, "ld3w", GPR64NoXZRshifted32>;
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def LD4W : sve_mem_eld_ss<0b10, 0b11, ZZZZ_s, "ld4w", GPR64NoXZRshifted32>;
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def LD2D : sve_mem_eld_ss<0b11, 0b01, ZZ_d, "ld2d", GPR64NoXZRshifted64>;
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def LD3D : sve_mem_eld_ss<0b11, 0b10, ZZZ_d, "ld3d", GPR64NoXZRshifted64>;
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def LD4D : sve_mem_eld_ss<0b11, 0b11, ZZZZ_d, "ld4d", GPR64NoXZRshifted64>;
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// Gathers using unscaled 32-bit offsets, e.g.
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// ld1h z0.s, p0/z, [x0, z0.s, uxtw]
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defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLDFF1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLD1W : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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// Gathers using scaled 32-bit offsets, e.g.
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// ld1h z0.s, p0/z, [x0, z0.s, uxtw #1]
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defm GLD1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm GLD1H_S : sve_mem_32b_gld_sv_32_scaled<0b0110, "ld1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm GLDFF1H_S : sve_mem_32b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm GLD1W : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
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defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
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// Gathers using scaled 32-bit pointers with offset, e.g.
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// ld1h z0.s, p0/z, [z0.s, #16]
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defm GLD1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0000, "ld1sb", imm0_31>;
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defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31>;
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defm GLD1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b", imm0_31>;
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defm GLDFF1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b", imm0_31>;
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defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2>;
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defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2>;
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defm GLD1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h", uimm5s2>;
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defm GLDFF1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0111, "ldff1h", uimm5s2>;
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defm GLD1W : sve_mem_32b_gld_vi_32_ptrs<0b1010, "ld1w", uimm5s4>;
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defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4>;
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// Gathers using scaled 64-bit pointers with offset, e.g.
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// ld1h z0.d, p0/z, [z0.d, #16]
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defm GLD1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0000, "ld1sb", imm0_31>;
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defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31>;
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defm GLD1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b", imm0_31>;
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defm GLDFF1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b", imm0_31>;
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defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2>;
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defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2>;
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defm GLD1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h", uimm5s2>;
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defm GLDFF1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0111, "ldff1h", uimm5s2>;
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defm GLD1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1000, "ld1sw", uimm5s4>;
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defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4>;
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defm GLD1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1010, "ld1w", uimm5s4>;
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defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4>;
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defm GLD1D : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d", uimm5s8>;
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defm GLDFF1D : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d", uimm5s8>;
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// Gathers using unscaled 64-bit offsets, e.g.
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// ld1h z0.d, p0/z, [x0, z0.d]
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defm GLD1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb">;
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defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb">;
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defm GLD1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0010, "ld1b">;
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defm GLDFF1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0011, "ldff1b">;
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defm GLD1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0100, "ld1sh">;
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defm GLDFF1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0101, "ldff1sh">;
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defm GLD1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0110, "ld1h">;
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defm GLDFF1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0111, "ldff1h">;
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defm GLD1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1000, "ld1sw">;
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defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw">;
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defm GLD1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1010, "ld1w">;
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defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w">;
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defm GLD1D : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d">;
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defm GLDFF1D : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d">;
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// Gathers using scaled 64-bit offsets, e.g.
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// ld1h z0.d, p0/z, [x0, z0.d, lsl #1]
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defm GLD1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0100, "ld1sh", ZPR64ExtLSL16>;
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defm GLDFF1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0101, "ldff1sh", ZPR64ExtLSL16>;
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defm GLD1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0110, "ld1h", ZPR64ExtLSL16>;
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defm GLDFF1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0111, "ldff1h", ZPR64ExtLSL16>;
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defm GLD1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw", ZPR64ExtLSL32>;
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defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>;
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defm GLD1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1010, "ld1w", ZPR64ExtLSL32>;
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defm GLDFF1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w", ZPR64ExtLSL32>;
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defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", ZPR64ExtLSL64>;
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defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", ZPR64ExtLSL64>;
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// Gathers using unscaled 32-bit offsets unpacked in 64-bits elements, e.g.
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// ld1h z0.d, p0/z, [x0, z0.d, uxtw]
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defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm GLD1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLD1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLD1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLD1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLD1D : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1D : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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// Gathers using scaled 32-bit offsets unpacked in 64-bits elements, e.g.
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// ld1h z0.d, p0/z, [x0, z0.d, uxtw #1]
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defm GLD1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm GLDFF1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0101, "ldff1sh",ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm GLD1H_D : sve_mem_64b_gld_sv_32_scaled<0b0110, "ld1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm GLDFF1H_D : sve_mem_64b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm GLD1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1000, "ld1sw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm GLDFF1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1001, "ldff1sw",ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm GLD1W_D : sve_mem_64b_gld_sv_32_scaled<0b1010, "ld1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm GLDFF1W_D : sve_mem_64b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm GLD1D : sve_mem_64b_gld_sv_32_scaled<0b1110, "ld1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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defm GLDFF1D : sve_mem_64b_gld_sv_32_scaled<0b1111, "ldff1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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// Non-temporal contiguous loads (register + immediate)
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defm LDNT1B_ZRI : sve_mem_cldnt_si<0b00, "ldnt1b", Z_b, ZPR8>;
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defm LDNT1H_ZRI : sve_mem_cldnt_si<0b01, "ldnt1h", Z_h, ZPR16>;
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defm LDNT1W_ZRI : sve_mem_cldnt_si<0b10, "ldnt1w", Z_s, ZPR32>;
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defm LDNT1D_ZRI : sve_mem_cldnt_si<0b11, "ldnt1d", Z_d, ZPR64>;
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// Non-temporal contiguous loads (register + register)
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defm LDNT1B_ZRR : sve_mem_cldnt_ss<0b00, "ldnt1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm LDNT1H_ZRR : sve_mem_cldnt_ss<0b01, "ldnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm LDNT1W_ZRR : sve_mem_cldnt_ss<0b10, "ldnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm LDNT1D_ZRR : sve_mem_cldnt_ss<0b11, "ldnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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// contiguous store with immediates
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defm ST1B_IMM : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
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defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
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defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>;
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defm ST1B_D_IMM : sve_mem_cst_si<0b00, 0b11, "st1b", Z_d, ZPR64>;
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defm ST1H_IMM : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>;
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defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>;
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defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>;
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defm ST1W_IMM : sve_mem_cst_si<0b10, 0b10, "st1w", Z_s, ZPR32>;
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defm ST1W_D_IMM : sve_mem_cst_si<0b10, 0b11, "st1w", Z_d, ZPR64>;
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defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>;
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// contiguous store with reg+reg addressing.
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defm ST1B : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm ST1B_H : sve_mem_cst_ss<0b0001, "st1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
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defm ST1B_S : sve_mem_cst_ss<0b0010, "st1b", Z_s, ZPR32, GPR64NoXZRshifted8>;
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defm ST1B_D : sve_mem_cst_ss<0b0011, "st1b", Z_d, ZPR64, GPR64NoXZRshifted8>;
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defm ST1H : sve_mem_cst_ss<0b0101, "st1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm ST1H_S : sve_mem_cst_ss<0b0110, "st1h", Z_s, ZPR32, GPR64NoXZRshifted16>;
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defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64NoXZRshifted16>;
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defm ST1W : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
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defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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// Scatters using unscaled 32-bit offsets, e.g.
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// st1h z0.s, p0, [x0, z0.s, uxtw]
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// and unpacked:
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// st1h z0.d, p0, [x0, z0.d, uxtw]
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defm SST1B_D : sve_mem_sst_sv_32_unscaled<0b000, "st1b", Z_d, ZPR64, ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm SST1B_S : sve_mem_sst_sv_32_unscaled<0b001, "st1b", Z_s, ZPR32, ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm SST1H_D : sve_mem_sst_sv_32_unscaled<0b010, "st1h", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm SST1H_S : sve_mem_sst_sv_32_unscaled<0b011, "st1h", Z_s, ZPR32, ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm SST1W_D : sve_mem_sst_sv_32_unscaled<0b100, "st1w", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm SST1W : sve_mem_sst_sv_32_unscaled<0b101, "st1w", Z_s, ZPR32, ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm SST1D : sve_mem_sst_sv_32_unscaled<0b110, "st1d", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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// Scatters using scaled 32-bit offsets, e.g.
|
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// st1h z0.s, p0, [x0, z0.s, uxtw #1]
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// and unpacked:
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// st1h z0.d, p0, [x0, z0.d, uxtw #1]
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defm SST1H_D : sve_mem_sst_sv_32_scaled<0b010, "st1h", Z_d, ZPR64, ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm SST1H_S : sve_mem_sst_sv_32_scaled<0b011, "st1h", Z_s, ZPR32, ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm SST1W_D : sve_mem_sst_sv_32_scaled<0b100, "st1w", Z_d, ZPR64, ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm SST1W : sve_mem_sst_sv_32_scaled<0b101, "st1w", Z_s, ZPR32, ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
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defm SST1D : sve_mem_sst_sv_32_scaled<0b110, "st1d", Z_d, ZPR64, ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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// Scatters using 32/64-bit pointers with offset, e.g.
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// st1h z0.s, p0, [z0.s, #16]
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// st1h z0.d, p0, [z0.d, #16]
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defm SST1B_D : sve_mem_sst_vi_ptrs<0b000, "st1b", Z_d, ZPR64, imm0_31>;
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defm SST1B_S : sve_mem_sst_vi_ptrs<0b001, "st1b", Z_s, ZPR32, imm0_31>;
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defm SST1H_D : sve_mem_sst_vi_ptrs<0b010, "st1h", Z_d, ZPR64, uimm5s2>;
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defm SST1H_S : sve_mem_sst_vi_ptrs<0b011, "st1h", Z_s, ZPR32, uimm5s2>;
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defm SST1W_D : sve_mem_sst_vi_ptrs<0b100, "st1w", Z_d, ZPR64, uimm5s4>;
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defm SST1W : sve_mem_sst_vi_ptrs<0b101, "st1w", Z_s, ZPR32, uimm5s4>;
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defm SST1D : sve_mem_sst_vi_ptrs<0b110, "st1d", Z_d, ZPR64, uimm5s8>;
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|
// Scatters using unscaled 64-bit offsets, e.g.
|
|
// st1h z0.d, p0, [x0, z0.d]
|
|
defm SST1B_D : sve_mem_sst_sv_64_unscaled<0b00, "st1b">;
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defm SST1H_D : sve_mem_sst_sv_64_unscaled<0b01, "st1h">;
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defm SST1W_D : sve_mem_sst_sv_64_unscaled<0b10, "st1w">;
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defm SST1D : sve_mem_sst_sv_64_unscaled<0b11, "st1d">;
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|
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// Scatters using scaled 64-bit offsets, e.g.
|
|
// st1h z0.d, p0, [x0, z0.d, lsl #1]
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defm SST1H_D_SCALED : sve_mem_sst_sv_64_scaled<0b01, "st1h", ZPR64ExtLSL16>;
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defm SST1W_D_SCALED : sve_mem_sst_sv_64_scaled<0b10, "st1w", ZPR64ExtLSL32>;
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defm SST1D_SCALED : sve_mem_sst_sv_64_scaled<0b11, "st1d", ZPR64ExtLSL64>;
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// ST(2|3|4) structured stores (register + immediate)
|
|
defm ST2B_IMM : sve_mem_est_si<0b00, 0b01, ZZ_b, "st2b", simm4s2>;
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defm ST3B_IMM : sve_mem_est_si<0b00, 0b10, ZZZ_b, "st3b", simm4s3>;
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defm ST4B_IMM : sve_mem_est_si<0b00, 0b11, ZZZZ_b, "st4b", simm4s4>;
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defm ST2H_IMM : sve_mem_est_si<0b01, 0b01, ZZ_h, "st2h", simm4s2>;
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defm ST3H_IMM : sve_mem_est_si<0b01, 0b10, ZZZ_h, "st3h", simm4s3>;
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defm ST4H_IMM : sve_mem_est_si<0b01, 0b11, ZZZZ_h, "st4h", simm4s4>;
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defm ST2W_IMM : sve_mem_est_si<0b10, 0b01, ZZ_s, "st2w", simm4s2>;
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defm ST3W_IMM : sve_mem_est_si<0b10, 0b10, ZZZ_s, "st3w", simm4s3>;
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defm ST4W_IMM : sve_mem_est_si<0b10, 0b11, ZZZZ_s, "st4w", simm4s4>;
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defm ST2D_IMM : sve_mem_est_si<0b11, 0b01, ZZ_d, "st2d", simm4s2>;
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defm ST3D_IMM : sve_mem_est_si<0b11, 0b10, ZZZ_d, "st3d", simm4s3>;
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defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>;
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// ST(2|3|4) structured stores (register + register)
|
|
def ST2B : sve_mem_est_ss<0b00, 0b01, ZZ_b, "st2b", GPR64NoXZRshifted8>;
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def ST3B : sve_mem_est_ss<0b00, 0b10, ZZZ_b, "st3b", GPR64NoXZRshifted8>;
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def ST4B : sve_mem_est_ss<0b00, 0b11, ZZZZ_b, "st4b", GPR64NoXZRshifted8>;
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def ST2H : sve_mem_est_ss<0b01, 0b01, ZZ_h, "st2h", GPR64NoXZRshifted16>;
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def ST3H : sve_mem_est_ss<0b01, 0b10, ZZZ_h, "st3h", GPR64NoXZRshifted16>;
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def ST4H : sve_mem_est_ss<0b01, 0b11, ZZZZ_h, "st4h", GPR64NoXZRshifted16>;
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def ST2W : sve_mem_est_ss<0b10, 0b01, ZZ_s, "st2w", GPR64NoXZRshifted32>;
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def ST3W : sve_mem_est_ss<0b10, 0b10, ZZZ_s, "st3w", GPR64NoXZRshifted32>;
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def ST4W : sve_mem_est_ss<0b10, 0b11, ZZZZ_s, "st4w", GPR64NoXZRshifted32>;
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def ST2D : sve_mem_est_ss<0b11, 0b01, ZZ_d, "st2d", GPR64NoXZRshifted64>;
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def ST3D : sve_mem_est_ss<0b11, 0b10, ZZZ_d, "st3d", GPR64NoXZRshifted64>;
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def ST4D : sve_mem_est_ss<0b11, 0b11, ZZZZ_d, "st4d", GPR64NoXZRshifted64>;
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|
// Non-temporal contiguous stores (register + immediate)
|
|
defm STNT1B_ZRI : sve_mem_cstnt_si<0b00, "stnt1b", Z_b, ZPR8>;
|
|
defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>;
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|
defm STNT1W_ZRI : sve_mem_cstnt_si<0b10, "stnt1w", Z_s, ZPR32>;
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|
defm STNT1D_ZRI : sve_mem_cstnt_si<0b11, "stnt1d", Z_d, ZPR64>;
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|
|
|
// Non-temporal contiguous stores (register + register)
|
|
defm STNT1B_ZRR : sve_mem_cstnt_ss<0b00, "stnt1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
|
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defm STNT1H_ZRR : sve_mem_cstnt_ss<0b01, "stnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm STNT1W_ZRR : sve_mem_cstnt_ss<0b10, "stnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm STNT1D_ZRR : sve_mem_cstnt_ss<0b11, "stnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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|
|
|
// Fill/Spill
|
|
defm LDR_ZXI : sve_mem_z_fill<"ldr">;
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defm LDR_PXI : sve_mem_p_fill<"ldr">;
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defm STR_ZXI : sve_mem_z_spill<"str">;
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defm STR_PXI : sve_mem_p_spill<"str">;
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|
|
// Contiguous prefetch (register + immediate)
|
|
defm PRFB_PRI : sve_mem_prfm_si<0b00, "prfb">;
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|
defm PRFH_PRI : sve_mem_prfm_si<0b01, "prfh">;
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defm PRFW_PRI : sve_mem_prfm_si<0b10, "prfw">;
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defm PRFD_PRI : sve_mem_prfm_si<0b11, "prfd">;
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|
|
// Contiguous prefetch (register + register)
|
|
def PRFB_PRR : sve_mem_prfm_ss<0b001, "prfb", GPR64NoXZRshifted8>;
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def PRFH_PRR : sve_mem_prfm_ss<0b011, "prfh", GPR64NoXZRshifted16>;
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def PRFS_PRR : sve_mem_prfm_ss<0b101, "prfw", GPR64NoXZRshifted32>;
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def PRFD_PRR : sve_mem_prfm_ss<0b111, "prfd", GPR64NoXZRshifted64>;
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|
|
// Gather prefetch using scaled 32-bit offsets, e.g.
|
|
// prfh pldl1keep, p0, [x0, z0.s, uxtw #1]
|
|
defm PRFB_S : sve_mem_32b_prfm_sv_scaled<0b00, "prfb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm PRFH_S : sve_mem_32b_prfm_sv_scaled<0b01, "prfh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm PRFW_S : sve_mem_32b_prfm_sv_scaled<0b10, "prfw", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
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defm PRFD_S : sve_mem_32b_prfm_sv_scaled<0b11, "prfd", ZPR32ExtSXTW64, ZPR32ExtUXTW64>;
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|
|
|
// Gather prefetch using unpacked, scaled 32-bit offsets, e.g.
|
|
// prfh pldl1keep, p0, [x0, z0.d, uxtw #1]
|
|
defm PRFB_D : sve_mem_64b_prfm_sv_ext_scaled<0b00, "prfb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
|
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defm PRFH_D : sve_mem_64b_prfm_sv_ext_scaled<0b01, "prfh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
|
|
defm PRFW_D : sve_mem_64b_prfm_sv_ext_scaled<0b10, "prfw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm PRFD_D : sve_mem_64b_prfm_sv_ext_scaled<0b11, "prfd", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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|
|
|
// Gather prefetch using scaled 64-bit offsets, e.g.
|
|
// prfh pldl1keep, p0, [x0, z0.d, lsl #1]
|
|
defm PRFB_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b00, "prfb", ZPR64ExtLSL8>;
|
|
defm PRFH_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b01, "prfh", ZPR64ExtLSL16>;
|
|
defm PRFW_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b10, "prfw", ZPR64ExtLSL32>;
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defm PRFD_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b11, "prfd", ZPR64ExtLSL64>;
|
|
|
|
// Gather prefetch using 32/64-bit pointers with offset, e.g.
|
|
// prfh pldl1keep, p0, [z0.s, #16]
|
|
// prfh pldl1keep, p0, [z0.d, #16]
|
|
defm PRFB_S_PZI : sve_mem_32b_prfm_vi<0b00, "prfb", imm0_31>;
|
|
defm PRFH_S_PZI : sve_mem_32b_prfm_vi<0b01, "prfh", uimm5s2>;
|
|
defm PRFW_S_PZI : sve_mem_32b_prfm_vi<0b10, "prfw", uimm5s4>;
|
|
defm PRFD_S_PZI : sve_mem_32b_prfm_vi<0b11, "prfd", uimm5s8>;
|
|
|
|
defm PRFB_D_PZI : sve_mem_64b_prfm_vi<0b00, "prfb", imm0_31>;
|
|
defm PRFH_D_PZI : sve_mem_64b_prfm_vi<0b01, "prfh", uimm5s2>;
|
|
defm PRFW_D_PZI : sve_mem_64b_prfm_vi<0b10, "prfw", uimm5s4>;
|
|
defm PRFD_D_PZI : sve_mem_64b_prfm_vi<0b11, "prfd", uimm5s8>;
|
|
|
|
defm ADR_SXTW_ZZZ_D : sve_int_bin_cons_misc_0_a_sxtw<0b00, "adr">;
|
|
defm ADR_UXTW_ZZZ_D : sve_int_bin_cons_misc_0_a_uxtw<0b01, "adr">;
|
|
defm ADR_LSL_ZZZ_S : sve_int_bin_cons_misc_0_a_32_lsl<0b10, "adr">;
|
|
defm ADR_LSL_ZZZ_D : sve_int_bin_cons_misc_0_a_64_lsl<0b11, "adr">;
|
|
|
|
defm TBL_ZZZ : sve_int_perm_tbl<"tbl">;
|
|
|
|
defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
|
|
defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
|
|
defm UZP1_ZZZ : sve_int_perm_bin_perm_zz<0b010, "uzp1">;
|
|
defm UZP2_ZZZ : sve_int_perm_bin_perm_zz<0b011, "uzp2">;
|
|
defm TRN1_ZZZ : sve_int_perm_bin_perm_zz<0b100, "trn1">;
|
|
defm TRN2_ZZZ : sve_int_perm_bin_perm_zz<0b101, "trn2">;
|
|
|
|
defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">;
|
|
defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
|
|
defm UZP1_PPP : sve_int_perm_bin_perm_pp<0b010, "uzp1">;
|
|
defm UZP2_PPP : sve_int_perm_bin_perm_pp<0b011, "uzp2">;
|
|
defm TRN1_PPP : sve_int_perm_bin_perm_pp<0b100, "trn1">;
|
|
defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2">;
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|
|
defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs">;
|
|
defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi">;
|
|
defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge">;
|
|
defm CMPGT_PPzZZ : sve_int_cmp_0<0b101, "cmpgt">;
|
|
defm CMPEQ_PPzZZ : sve_int_cmp_0<0b110, "cmpeq">;
|
|
defm CMPNE_PPzZZ : sve_int_cmp_0<0b111, "cmpne">;
|
|
|
|
defm CMPEQ_WIDE_PPzZZ : sve_int_cmp_0_wide<0b010, "cmpeq">;
|
|
defm CMPNE_WIDE_PPzZZ : sve_int_cmp_0_wide<0b011, "cmpne">;
|
|
defm CMPGE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b000, "cmpge">;
|
|
defm CMPGT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b001, "cmpgt">;
|
|
defm CMPLT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b010, "cmplt">;
|
|
defm CMPLE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b011, "cmple">;
|
|
defm CMPHS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b100, "cmphs">;
|
|
defm CMPHI_WIDE_PPzZZ : sve_int_cmp_1_wide<0b101, "cmphi">;
|
|
defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;
|
|
defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;
|
|
|
|
defm CMPGE_PPzZI : sve_int_scmp_vi<0b000, "cmpge">;
|
|
defm CMPGT_PPzZI : sve_int_scmp_vi<0b001, "cmpgt">;
|
|
defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt">;
|
|
defm CMPLE_PPzZI : sve_int_scmp_vi<0b011, "cmple">;
|
|
defm CMPEQ_PPzZI : sve_int_scmp_vi<0b100, "cmpeq">;
|
|
defm CMPNE_PPzZI : sve_int_scmp_vi<0b101, "cmpne">;
|
|
defm CMPHS_PPzZI : sve_int_ucmp_vi<0b00, "cmphs">;
|
|
defm CMPHI_PPzZI : sve_int_ucmp_vi<0b01, "cmphi">;
|
|
defm CMPLO_PPzZI : sve_int_ucmp_vi<0b10, "cmplo">;
|
|
defm CMPLS_PPzZI : sve_int_ucmp_vi<0b11, "cmpls">;
|
|
|
|
defm FCMGE_PPzZZ : sve_fp_3op_p_pd<0b000, "fcmge">;
|
|
defm FCMGT_PPzZZ : sve_fp_3op_p_pd<0b001, "fcmgt">;
|
|
defm FCMEQ_PPzZZ : sve_fp_3op_p_pd<0b010, "fcmeq">;
|
|
defm FCMNE_PPzZZ : sve_fp_3op_p_pd<0b011, "fcmne">;
|
|
defm FCMUO_PPzZZ : sve_fp_3op_p_pd<0b100, "fcmuo">;
|
|
defm FACGE_PPzZZ : sve_fp_3op_p_pd<0b101, "facge">;
|
|
defm FACGT_PPzZZ : sve_fp_3op_p_pd<0b111, "facgt">;
|
|
|
|
defm FCMGE_PPzZ0 : sve_fp_2op_p_pd<0b000, "fcmge">;
|
|
defm FCMGT_PPzZ0 : sve_fp_2op_p_pd<0b001, "fcmgt">;
|
|
defm FCMLT_PPzZ0 : sve_fp_2op_p_pd<0b010, "fcmlt">;
|
|
defm FCMLE_PPzZ0 : sve_fp_2op_p_pd<0b011, "fcmle">;
|
|
defm FCMEQ_PPzZ0 : sve_fp_2op_p_pd<0b100, "fcmeq">;
|
|
defm FCMNE_PPzZ0 : sve_fp_2op_p_pd<0b110, "fcmne">;
|
|
|
|
defm WHILELT_PWW : sve_int_while4_rr<0b010, "whilelt">;
|
|
defm WHILELE_PWW : sve_int_while4_rr<0b011, "whilele">;
|
|
defm WHILELO_PWW : sve_int_while4_rr<0b110, "whilelo">;
|
|
defm WHILELS_PWW : sve_int_while4_rr<0b111, "whilels">;
|
|
|
|
defm WHILELT_PXX : sve_int_while8_rr<0b010, "whilelt">;
|
|
defm WHILELE_PXX : sve_int_while8_rr<0b011, "whilele">;
|
|
defm WHILELO_PXX : sve_int_while8_rr<0b110, "whilelo">;
|
|
defm WHILELS_PXX : sve_int_while8_rr<0b111, "whilels">;
|
|
|
|
def CTERMEQ_WW : sve_int_cterm<0b0, 0b0, "ctermeq", GPR32>;
|
|
def CTERMNE_WW : sve_int_cterm<0b0, 0b1, "ctermne", GPR32>;
|
|
def CTERMEQ_XX : sve_int_cterm<0b1, 0b0, "ctermeq", GPR64>;
|
|
def CTERMNE_XX : sve_int_cterm<0b1, 0b1, "ctermne", GPR64>;
|
|
|
|
def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;
|
|
def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;
|
|
def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">;
|
|
|
|
defm CNTB_XPiI : sve_int_count<0b000, "cntb">;
|
|
defm CNTH_XPiI : sve_int_count<0b010, "cnth">;
|
|
defm CNTW_XPiI : sve_int_count<0b100, "cntw">;
|
|
defm CNTD_XPiI : sve_int_count<0b110, "cntd">;
|
|
defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp">;
|
|
|
|
defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb">;
|
|
defm DECB_XPiI : sve_int_pred_pattern_a<0b001, "decb">;
|
|
defm INCH_XPiI : sve_int_pred_pattern_a<0b010, "inch">;
|
|
defm DECH_XPiI : sve_int_pred_pattern_a<0b011, "dech">;
|
|
defm INCW_XPiI : sve_int_pred_pattern_a<0b100, "incw">;
|
|
defm DECW_XPiI : sve_int_pred_pattern_a<0b101, "decw">;
|
|
defm INCD_XPiI : sve_int_pred_pattern_a<0b110, "incd">;
|
|
defm DECD_XPiI : sve_int_pred_pattern_a<0b111, "decd">;
|
|
|
|
defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<0b00000, "sqincb">;
|
|
defm UQINCB_WPiI : sve_int_pred_pattern_b_u32<0b00001, "uqincb">;
|
|
defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<0b00010, "sqdecb">;
|
|
defm UQDECB_WPiI : sve_int_pred_pattern_b_u32<0b00011, "uqdecb">;
|
|
defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">;
|
|
defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">;
|
|
defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">;
|
|
defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">;
|
|
|
|
defm SQINCH_XPiWdI : sve_int_pred_pattern_b_s32<0b01000, "sqinch">;
|
|
defm UQINCH_WPiI : sve_int_pred_pattern_b_u32<0b01001, "uqinch">;
|
|
defm SQDECH_XPiWdI : sve_int_pred_pattern_b_s32<0b01010, "sqdech">;
|
|
defm UQDECH_WPiI : sve_int_pred_pattern_b_u32<0b01011, "uqdech">;
|
|
defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">;
|
|
defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">;
|
|
defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">;
|
|
defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">;
|
|
|
|
defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw">;
|
|
defm UQINCW_WPiI : sve_int_pred_pattern_b_u32<0b10001, "uqincw">;
|
|
defm SQDECW_XPiWdI : sve_int_pred_pattern_b_s32<0b10010, "sqdecw">;
|
|
defm UQDECW_WPiI : sve_int_pred_pattern_b_u32<0b10011, "uqdecw">;
|
|
defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">;
|
|
defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">;
|
|
defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">;
|
|
defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">;
|
|
|
|
defm SQINCD_XPiWdI : sve_int_pred_pattern_b_s32<0b11000, "sqincd">;
|
|
defm UQINCD_WPiI : sve_int_pred_pattern_b_u32<0b11001, "uqincd">;
|
|
defm SQDECD_XPiWdI : sve_int_pred_pattern_b_s32<0b11010, "sqdecd">;
|
|
defm UQDECD_WPiI : sve_int_pred_pattern_b_u32<0b11011, "uqdecd">;
|
|
defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">;
|
|
defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">;
|
|
defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
|
|
defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">;
|
|
|
|
defm SQINCH_ZPiI : sve_int_countvlv<0b01000, "sqinch", ZPR16>;
|
|
defm UQINCH_ZPiI : sve_int_countvlv<0b01001, "uqinch", ZPR16>;
|
|
defm SQDECH_ZPiI : sve_int_countvlv<0b01010, "sqdech", ZPR16>;
|
|
defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16>;
|
|
defm INCH_ZPiI : sve_int_countvlv<0b01100, "inch", ZPR16>;
|
|
defm DECH_ZPiI : sve_int_countvlv<0b01101, "dech", ZPR16>;
|
|
defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32>;
|
|
defm UQINCW_ZPiI : sve_int_countvlv<0b10001, "uqincw", ZPR32>;
|
|
defm SQDECW_ZPiI : sve_int_countvlv<0b10010, "sqdecw", ZPR32>;
|
|
defm UQDECW_ZPiI : sve_int_countvlv<0b10011, "uqdecw", ZPR32>;
|
|
defm INCW_ZPiI : sve_int_countvlv<0b10100, "incw", ZPR32>;
|
|
defm DECW_ZPiI : sve_int_countvlv<0b10101, "decw", ZPR32>;
|
|
defm SQINCD_ZPiI : sve_int_countvlv<0b11000, "sqincd", ZPR64>;
|
|
defm UQINCD_ZPiI : sve_int_countvlv<0b11001, "uqincd", ZPR64>;
|
|
defm SQDECD_ZPiI : sve_int_countvlv<0b11010, "sqdecd", ZPR64>;
|
|
defm UQDECD_ZPiI : sve_int_countvlv<0b11011, "uqdecd", ZPR64>;
|
|
defm INCD_ZPiI : sve_int_countvlv<0b11100, "incd", ZPR64>;
|
|
defm DECD_ZPiI : sve_int_countvlv<0b11101, "decd", ZPR64>;
|
|
|
|
defm SQINCP_XPWd : sve_int_count_r_s32<0b00000, "sqincp">;
|
|
defm SQINCP_XP : sve_int_count_r_x64<0b00010, "sqincp">;
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defm UQINCP_WP : sve_int_count_r_u32<0b00100, "uqincp">;
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|
defm UQINCP_XP : sve_int_count_r_x64<0b00110, "uqincp">;
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defm SQDECP_XPWd : sve_int_count_r_s32<0b01000, "sqdecp">;
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defm SQDECP_XP : sve_int_count_r_x64<0b01010, "sqdecp">;
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defm UQDECP_WP : sve_int_count_r_u32<0b01100, "uqdecp">;
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defm UQDECP_XP : sve_int_count_r_x64<0b01110, "uqdecp">;
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defm INCP_XP : sve_int_count_r_x64<0b10000, "incp">;
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defm DECP_XP : sve_int_count_r_x64<0b10100, "decp">;
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defm SQINCP_ZP : sve_int_count_v<0b00000, "sqincp">;
|
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defm UQINCP_ZP : sve_int_count_v<0b00100, "uqincp">;
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defm SQDECP_ZP : sve_int_count_v<0b01000, "sqdecp">;
|
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defm UQDECP_ZP : sve_int_count_v<0b01100, "uqdecp">;
|
|
defm INCP_ZP : sve_int_count_v<0b10000, "incp">;
|
|
defm DECP_ZP : sve_int_count_v<0b10100, "decp">;
|
|
|
|
defm INDEX_RR : sve_int_index_rr<"index">;
|
|
defm INDEX_IR : sve_int_index_ir<"index">;
|
|
defm INDEX_RI : sve_int_index_ri<"index">;
|
|
defm INDEX_II : sve_int_index_ii<"index">;
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|
|
|
// Unpredicated shifts
|
|
defm ASR_ZZI : sve_int_bin_cons_shift_imm_right<0b00, "asr">;
|
|
defm LSR_ZZI : sve_int_bin_cons_shift_imm_right<0b01, "lsr">;
|
|
defm LSL_ZZI : sve_int_bin_cons_shift_imm_left< 0b11, "lsl">;
|
|
|
|
defm ASR_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b00, "asr">;
|
|
defm LSR_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b01, "lsr">;
|
|
defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">;
|
|
|
|
// Predicated shifts
|
|
defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0000, "asr">;
|
|
defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0001, "lsr">;
|
|
defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0011, "lsl">;
|
|
defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b0100, "asrd">;
|
|
|
|
defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">;
|
|
defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">;
|
|
defm LSL_ZPmZ : sve_int_bin_pred_shift<0b011, "lsl">;
|
|
defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr">;
|
|
defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr">;
|
|
defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr">;
|
|
|
|
defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr">;
|
|
defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr">;
|
|
defm LSL_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b011, "lsl">;
|
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|
|
def FCVT_ZPmZ_StoH : sve_fp_2op_p_zd<0b1001000, "fcvt", ZPR32, ZPR16, ElementSizeS>;
|
|
def FCVT_ZPmZ_HtoS : sve_fp_2op_p_zd<0b1001001, "fcvt", ZPR16, ZPR32, ElementSizeS>;
|
|
def SCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110010, "scvtf", ZPR16, ZPR16, ElementSizeH>;
|
|
def SCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010100, "scvtf", ZPR32, ZPR32, ElementSizeS>;
|
|
def UCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010101, "ucvtf", ZPR32, ZPR32, ElementSizeS>;
|
|
def UCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110011, "ucvtf", ZPR16, ZPR16, ElementSizeH>;
|
|
def FCVTZS_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111010, "fcvtzs", ZPR16, ZPR16, ElementSizeH>;
|
|
def FCVTZS_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011100, "fcvtzs", ZPR32, ZPR32, ElementSizeS>;
|
|
def FCVTZU_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111011, "fcvtzu", ZPR16, ZPR16, ElementSizeH>;
|
|
def FCVTZU_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011101, "fcvtzu", ZPR32, ZPR32, ElementSizeS>;
|
|
def FCVT_ZPmZ_DtoH : sve_fp_2op_p_zd<0b1101000, "fcvt", ZPR64, ZPR16, ElementSizeD>;
|
|
def FCVT_ZPmZ_HtoD : sve_fp_2op_p_zd<0b1101001, "fcvt", ZPR16, ZPR64, ElementSizeD>;
|
|
def FCVT_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1101010, "fcvt", ZPR64, ZPR32, ElementSizeD>;
|
|
def FCVT_ZPmZ_StoD : sve_fp_2op_p_zd<0b1101011, "fcvt", ZPR32, ZPR64, ElementSizeD>;
|
|
def SCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110000, "scvtf", ZPR32, ZPR64, ElementSizeD>;
|
|
def UCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110001, "ucvtf", ZPR32, ZPR64, ElementSizeD>;
|
|
def UCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110101, "ucvtf", ZPR32, ZPR16, ElementSizeS>;
|
|
def SCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110100, "scvtf", ZPR64, ZPR32, ElementSizeD>;
|
|
def SCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110100, "scvtf", ZPR32, ZPR16, ElementSizeS>;
|
|
def SCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110110, "scvtf", ZPR64, ZPR16, ElementSizeD>;
|
|
def UCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110101, "ucvtf", ZPR64, ZPR32, ElementSizeD>;
|
|
def UCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110111, "ucvtf", ZPR64, ZPR16, ElementSizeD>;
|
|
def SCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110110, "scvtf", ZPR64, ZPR64, ElementSizeD>;
|
|
def UCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110111, "ucvtf", ZPR64, ZPR64, ElementSizeD>;
|
|
def FCVTZS_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111000, "fcvtzs", ZPR64, ZPR32, ElementSizeD>;
|
|
def FCVTZU_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111001, "fcvtzu", ZPR64, ZPR32, ElementSizeD>;
|
|
def FCVTZS_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111100, "fcvtzs", ZPR32, ZPR64, ElementSizeD>;
|
|
def FCVTZS_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111100, "fcvtzs", ZPR16, ZPR32, ElementSizeS>;
|
|
def FCVTZS_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111110, "fcvtzs", ZPR16, ZPR64, ElementSizeD>;
|
|
def FCVTZU_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111101, "fcvtzu", ZPR16, ZPR32, ElementSizeS>;
|
|
def FCVTZU_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111111, "fcvtzu", ZPR16, ZPR64, ElementSizeD>;
|
|
def FCVTZU_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111101, "fcvtzu", ZPR32, ZPR64, ElementSizeD>;
|
|
def FCVTZS_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111110, "fcvtzs", ZPR64, ZPR64, ElementSizeD>;
|
|
def FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111111, "fcvtzu", ZPR64, ZPR64, ElementSizeD>;
|
|
|
|
defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn">;
|
|
defm FRINTP_ZPmZ : sve_fp_2op_p_zd_HSD<0b00001, "frintp">;
|
|
defm FRINTM_ZPmZ : sve_fp_2op_p_zd_HSD<0b00010, "frintm">;
|
|
defm FRINTZ_ZPmZ : sve_fp_2op_p_zd_HSD<0b00011, "frintz">;
|
|
defm FRINTA_ZPmZ : sve_fp_2op_p_zd_HSD<0b00100, "frinta">;
|
|
defm FRINTX_ZPmZ : sve_fp_2op_p_zd_HSD<0b00110, "frintx">;
|
|
defm FRINTI_ZPmZ : sve_fp_2op_p_zd_HSD<0b00111, "frinti">;
|
|
defm FRECPX_ZPmZ : sve_fp_2op_p_zd_HSD<0b01100, "frecpx">;
|
|
defm FSQRT_ZPmZ : sve_fp_2op_p_zd_HSD<0b01101, "fsqrt">;
|
|
|
|
// InstAliases
|
|
def : InstAlias<"mov $Zd, $Zn",
|
|
(ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
|
|
def : InstAlias<"mov $Pd, $Pg/m, $Pn",
|
|
(SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>;
|
|
def : InstAlias<"mov $Pd, $Pn",
|
|
(ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
|
|
def : InstAlias<"mov $Pd, $Pg/z, $Pn",
|
|
(AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
|
|
|
|
def : InstAlias<"movs $Pd, $Pn",
|
|
(ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
|
|
def : InstAlias<"movs $Pd, $Pg/z, $Pn",
|
|
(ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
|
|
|
|
def : InstAlias<"not $Pd, $Pg/z, $Pn",
|
|
(EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
|
|
|
|
def : InstAlias<"nots $Pd, $Pg/z, $Pn",
|
|
(EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
|
|
|
|
def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPGE_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
|
|
def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
|
|
def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
|
|
def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
|
|
|
|
def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPHI_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
|
|
def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPHI_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
|
|
def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPHI_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
|
|
def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPHI_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
|
|
|
|
def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPHS_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
|
|
def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPHS_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
|
|
def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPHS_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
|
|
def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPHS_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
|
|
|
|
def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPGT_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
|
|
def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
|
|
def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
|
|
def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
|
|
(CMPGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
|
|
|
|
def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
|
|
(FACGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
|
|
def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
|
|
(FACGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
|
|
def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
|
|
(FACGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
|
|
|
|
def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
|
|
(FACGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
|
|
def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
|
|
(FACGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
|
|
def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
|
|
(FACGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
|
|
|
|
def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
|
|
(FCMGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
|
|
def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
|
|
(FCMGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
|
|
def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
|
|
(FCMGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
|
|
|
|
def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
|
|
(FCMGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
|
|
def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
|
|
(FCMGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
|
|
def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
|
|
(FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
|
|
}
|
|
|
|
let Predicates = [HasSVE2] in {
|
|
// SVE2 integer multiply-add (indexed)
|
|
defm MLA_ZZZI : sve2_int_mla_by_indexed_elem<0b01, 0b0, "mla">;
|
|
defm MLS_ZZZI : sve2_int_mla_by_indexed_elem<0b01, 0b1, "mls">;
|
|
|
|
// SVE2 saturating multiply-add high (indexed)
|
|
defm SQRDMLAH_ZZZI : sve2_int_mla_by_indexed_elem<0b10, 0b0, "sqrdmlah">;
|
|
defm SQRDMLSH_ZZZI : sve2_int_mla_by_indexed_elem<0b10, 0b1, "sqrdmlsh">;
|
|
|
|
// SVE2 saturating multiply-add high (vectors, unpredicated)
|
|
defm SQRDMLAH_ZZZ : sve2_int_mla<0b0, "sqrdmlah">;
|
|
defm SQRDMLSH_ZZZ : sve2_int_mla<0b1, "sqrdmlsh">;
|
|
|
|
// SVE2 integer multiply (indexed)
|
|
defm MUL_ZZZI : sve2_int_mul_by_indexed_elem<0b1110, "mul">;
|
|
|
|
// SVE2 saturating multiply high (indexed)
|
|
defm SQDMULH_ZZZI : sve2_int_mul_by_indexed_elem<0b1100, "sqdmulh">;
|
|
defm SQRDMULH_ZZZI : sve2_int_mul_by_indexed_elem<0b1101, "sqrdmulh">;
|
|
|
|
// SVE2 signed saturating doubling multiply high (unpredicated)
|
|
defm SQDMULH_ZZZ : sve2_int_mul<0b100, "sqdmulh">;
|
|
defm SQRDMULH_ZZZ : sve2_int_mul<0b101, "sqrdmulh">;
|
|
|
|
// SVE2 integer multiply vectors (unpredicated)
|
|
defm MUL_ZZZ : sve2_int_mul<0b000, "mul">;
|
|
defm SMULH_ZZZ : sve2_int_mul<0b010, "smulh">;
|
|
defm UMULH_ZZZ : sve2_int_mul<0b011, "umulh">;
|
|
def PMUL_ZZZ_B : sve2_int_mul<0b00, 0b001, "pmul", ZPR8>;
|
|
|
|
// SVE2 complex integer dot product (indexed)
|
|
defm CDOT_ZZZI : sve2_cintx_dot_by_indexed_elem<"cdot">;
|
|
|
|
// SVE2 complex integer dot product
|
|
defm CDOT_ZZZ : sve2_cintx_dot<"cdot">;
|
|
|
|
// SVE2 complex integer multiply-add (indexed)
|
|
defm CMLA_ZZZI : sve2_cmla_by_indexed_elem<0b0, "cmla">;
|
|
// SVE2 complex saturating multiply-add (indexed)
|
|
defm SQRDCMLAH_ZZZI : sve2_cmla_by_indexed_elem<0b1, "sqrdcmlah">;
|
|
|
|
// SVE2 complex integer multiply-add
|
|
defm CMLA_ZZZ : sve2_int_cmla<0b0, "cmla">;
|
|
defm SQRDCMLAH_ZZZ : sve2_int_cmla<0b1, "sqrdcmlah">;
|
|
|
|
// SVE2 integer multiply long (indexed)
|
|
defm SMULLB_ZZZI : sve2_int_mul_long_by_indexed_elem<0b000, "smullb">;
|
|
defm SMULLT_ZZZI : sve2_int_mul_long_by_indexed_elem<0b001, "smullt">;
|
|
defm UMULLB_ZZZI : sve2_int_mul_long_by_indexed_elem<0b010, "umullb">;
|
|
defm UMULLT_ZZZI : sve2_int_mul_long_by_indexed_elem<0b011, "umullt">;
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// SVE2 saturating multiply (indexed)
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defm SQDMULLB_ZZZI : sve2_int_mul_long_by_indexed_elem<0b100, "sqdmullb">;
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defm SQDMULLT_ZZZI : sve2_int_mul_long_by_indexed_elem<0b101, "sqdmullt">;
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// SVE2 integer multiply-add long (indexed)
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defm SMLALB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1000, "smlalb">;
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defm SMLALT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1001, "smlalt">;
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defm UMLALB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1010, "umlalb">;
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defm UMLALT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1011, "umlalt">;
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defm SMLSLB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1100, "smlslb">;
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defm SMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1101, "smlslt">;
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defm UMLSLB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1110, "umlslb">;
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defm UMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1111, "umlslt">;
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// SVE2 integer multiply-add long (vectors, unpredicated)
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defm SMLALB_ZZZ : sve2_int_mla_long<0b10000, "smlalb">;
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defm SMLALT_ZZZ : sve2_int_mla_long<0b10001, "smlalt">;
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defm UMLALB_ZZZ : sve2_int_mla_long<0b10010, "umlalb">;
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defm UMLALT_ZZZ : sve2_int_mla_long<0b10011, "umlalt">;
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defm SMLSLB_ZZZ : sve2_int_mla_long<0b10100, "smlslb">;
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defm SMLSLT_ZZZ : sve2_int_mla_long<0b10101, "smlslt">;
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defm UMLSLB_ZZZ : sve2_int_mla_long<0b10110, "umlslb">;
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defm UMLSLT_ZZZ : sve2_int_mla_long<0b10111, "umlslt">;
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// SVE2 saturating multiply-add long (indexed)
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defm SQDMLALB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b0100, "sqdmlalb">;
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defm SQDMLALT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b0101, "sqdmlalt">;
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defm SQDMLSLB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b0110, "sqdmlslb">;
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defm SQDMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b0111, "sqdmlslt">;
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// SVE2 saturating multiply-add long (vectors, unpredicated)
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defm SQDMLALB_ZZZ : sve2_int_mla_long<0b11000, "sqdmlalb">;
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defm SQDMLALT_ZZZ : sve2_int_mla_long<0b11001, "sqdmlalt">;
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defm SQDMLSLB_ZZZ : sve2_int_mla_long<0b11010, "sqdmlslb">;
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defm SQDMLSLT_ZZZ : sve2_int_mla_long<0b11011, "sqdmlslt">;
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// SVE2 saturating multiply-add interleaved long
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defm SQDMLALBT_ZZZ : sve2_int_mla_long<0b00010, "sqdmlalbt">;
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defm SQDMLSLBT_ZZZ : sve2_int_mla_long<0b00011, "sqdmlslbt">;
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// SVE2 integer halving add/subtract (predicated)
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defm SHADD_ZPmZ : sve2_int_arith_pred<0b100000, "shadd">;
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defm UHADD_ZPmZ : sve2_int_arith_pred<0b100010, "uhadd">;
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defm SHSUB_ZPmZ : sve2_int_arith_pred<0b100100, "shsub">;
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defm UHSUB_ZPmZ : sve2_int_arith_pred<0b100110, "uhsub">;
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defm SRHADD_ZPmZ : sve2_int_arith_pred<0b101000, "srhadd">;
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defm URHADD_ZPmZ : sve2_int_arith_pred<0b101010, "urhadd">;
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defm SHSUBR_ZPmZ : sve2_int_arith_pred<0b101100, "shsubr">;
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defm UHSUBR_ZPmZ : sve2_int_arith_pred<0b101110, "uhsubr">;
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// SVE2 integer pairwise add and accumulate long
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defm SADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<0, "sadalp">;
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defm UADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<1, "uadalp">;
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// SVE2 integer pairwise arithmetic
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defm ADDP_ZPmZ : sve2_int_arith_pred<0b100011, "addp">;
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defm SMAXP_ZPmZ : sve2_int_arith_pred<0b101001, "smaxp">;
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defm UMAXP_ZPmZ : sve2_int_arith_pred<0b101011, "umaxp">;
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defm SMINP_ZPmZ : sve2_int_arith_pred<0b101101, "sminp">;
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defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp">;
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// SVE2 integer unary operations (predicated)
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defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b000, "urecpe">;
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defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b001, "ursqrte">;
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defm SQABS_ZPmZ : sve2_int_un_pred_arit<0b100, "sqabs">;
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defm SQNEG_ZPmZ : sve2_int_un_pred_arit<0b101, "sqneg">;
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// SVE2 saturating add/subtract
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defm SQADD_ZPmZ : sve2_int_arith_pred<0b110000, "sqadd">;
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defm UQADD_ZPmZ : sve2_int_arith_pred<0b110010, "uqadd">;
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defm SQSUB_ZPmZ : sve2_int_arith_pred<0b110100, "sqsub">;
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defm UQSUB_ZPmZ : sve2_int_arith_pred<0b110110, "uqsub">;
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defm SUQADD_ZPmZ : sve2_int_arith_pred<0b111000, "suqadd">;
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defm USQADD_ZPmZ : sve2_int_arith_pred<0b111010, "usqadd">;
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defm SQSUBR_ZPmZ : sve2_int_arith_pred<0b111100, "sqsubr">;
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defm UQSUBR_ZPmZ : sve2_int_arith_pred<0b111110, "uqsubr">;
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// SVE2 saturating/rounding bitwise shift left (predicated)
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defm SRSHL_ZPmZ : sve2_int_arith_pred<0b000100, "srshl">;
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defm URSHL_ZPmZ : sve2_int_arith_pred<0b000110, "urshl">;
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defm SRSHLR_ZPmZ : sve2_int_arith_pred<0b001100, "srshlr">;
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defm URSHLR_ZPmZ : sve2_int_arith_pred<0b001110, "urshlr">;
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defm SQSHL_ZPmZ : sve2_int_arith_pred<0b010000, "sqshl">;
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defm UQSHL_ZPmZ : sve2_int_arith_pred<0b010010, "uqshl">;
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defm SQRSHL_ZPmZ : sve2_int_arith_pred<0b010100, "sqrshl">;
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defm UQRSHL_ZPmZ : sve2_int_arith_pred<0b010110, "uqrshl">;
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defm SQSHLR_ZPmZ : sve2_int_arith_pred<0b011000, "sqshlr">;
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defm UQSHLR_ZPmZ : sve2_int_arith_pred<0b011010, "uqshlr">;
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defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr">;
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defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr">;
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// SVE2 predicated shifts
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defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
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defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
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defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
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defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
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defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
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// SVE2 integer add/subtract long
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defm SADDLB_ZZZ : sve2_wide_int_arith_long<0b00000, "saddlb">;
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defm SADDLT_ZZZ : sve2_wide_int_arith_long<0b00001, "saddlt">;
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defm UADDLB_ZZZ : sve2_wide_int_arith_long<0b00010, "uaddlb">;
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defm UADDLT_ZZZ : sve2_wide_int_arith_long<0b00011, "uaddlt">;
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defm SSUBLB_ZZZ : sve2_wide_int_arith_long<0b00100, "ssublb">;
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defm SSUBLT_ZZZ : sve2_wide_int_arith_long<0b00101, "ssublt">;
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defm USUBLB_ZZZ : sve2_wide_int_arith_long<0b00110, "usublb">;
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defm USUBLT_ZZZ : sve2_wide_int_arith_long<0b00111, "usublt">;
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defm SABDLB_ZZZ : sve2_wide_int_arith_long<0b01100, "sabdlb">;
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defm SABDLT_ZZZ : sve2_wide_int_arith_long<0b01101, "sabdlt">;
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defm UABDLB_ZZZ : sve2_wide_int_arith_long<0b01110, "uabdlb">;
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defm UABDLT_ZZZ : sve2_wide_int_arith_long<0b01111, "uabdlt">;
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// SVE2 integer add/subtract wide
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defm SADDWB_ZZZ : sve2_wide_int_arith_wide<0b000, "saddwb">;
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defm SADDWT_ZZZ : sve2_wide_int_arith_wide<0b001, "saddwt">;
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defm UADDWB_ZZZ : sve2_wide_int_arith_wide<0b010, "uaddwb">;
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defm UADDWT_ZZZ : sve2_wide_int_arith_wide<0b011, "uaddwt">;
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defm SSUBWB_ZZZ : sve2_wide_int_arith_wide<0b100, "ssubwb">;
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defm SSUBWT_ZZZ : sve2_wide_int_arith_wide<0b101, "ssubwt">;
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defm USUBWB_ZZZ : sve2_wide_int_arith_wide<0b110, "usubwb">;
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defm USUBWT_ZZZ : sve2_wide_int_arith_wide<0b111, "usubwt">;
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// SVE2 integer multiply long
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defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">;
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defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">;
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defm SMULLB_ZZZ : sve2_wide_int_arith_long<0b11100, "smullb">;
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defm SMULLT_ZZZ : sve2_wide_int_arith_long<0b11101, "smullt">;
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defm UMULLB_ZZZ : sve2_wide_int_arith_long<0b11110, "umullb">;
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defm UMULLT_ZZZ : sve2_wide_int_arith_long<0b11111, "umullt">;
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defm PMULLB_ZZZ : sve2_pmul_long<0b0, "pmullb">;
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defm PMULLT_ZZZ : sve2_pmul_long<0b1, "pmullt">;
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// SVE2 bitwise shift and insert
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defm SRI_ZZI : sve2_int_bin_shift_imm_right<0b0, "sri">;
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defm SLI_ZZI : sve2_int_bin_shift_imm_left< 0b1, "sli">;
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// SVE2 bitwise shift right and accumulate
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defm SSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b00, "ssra">;
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defm USRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b01, "usra">;
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defm SRSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b10, "srsra">;
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defm URSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b11, "ursra">;
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// SVE2 complex integer add
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defm CADD_ZZI : sve2_int_cadd<0b0, "cadd">;
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defm SQCADD_ZZI : sve2_int_cadd<0b1, "sqcadd">;
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// SVE2 integer absolute difference and accumulate
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defm SABA_ZZZ : sve2_int_absdiff_accum<0b0, "saba">;
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defm UABA_ZZZ : sve2_int_absdiff_accum<0b1, "uaba">;
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// SVE2 integer absolute difference and accumulate long
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defm SABALB_ZZZ : sve2_int_absdiff_accum_long<0b00, "sabalb">;
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defm SABALT_ZZZ : sve2_int_absdiff_accum_long<0b01, "sabalt">;
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defm UABALB_ZZZ : sve2_int_absdiff_accum_long<0b10, "uabalb">;
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defm UABALT_ZZZ : sve2_int_absdiff_accum_long<0b11, "uabalt">;
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// SVE2 integer add/subtract long with carry
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defm ADCLB_ZZZ : sve2_int_addsub_long_carry<0b00, "adclb">;
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defm ADCLT_ZZZ : sve2_int_addsub_long_carry<0b01, "adclt">;
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defm SBCLB_ZZZ : sve2_int_addsub_long_carry<0b10, "sbclb">;
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defm SBCLT_ZZZ : sve2_int_addsub_long_carry<0b11, "sbclt">;
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// SVE2 bitwise shift right narrow (bottom)
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defm SQSHRUNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b000, "sqshrunb">;
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defm SQRSHRUNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b001, "sqrshrunb">;
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defm SHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b010, "shrnb">;
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defm RSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b011, "rshrnb">;
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defm SQSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b100, "sqshrnb">;
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defm SQRSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b101, "sqrshrnb">;
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defm UQSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b110, "uqshrnb">;
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defm UQRSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b111, "uqrshrnb">;
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// SVE2 bitwise shift right narrow (top)
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defm SQSHRUNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b000, "sqshrunt">;
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defm SQRSHRUNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b001, "sqrshrunt">;
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defm SHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b010, "shrnt">;
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defm RSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b011, "rshrnt">;
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defm SQSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b100, "sqshrnt">;
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defm SQRSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b101, "sqrshrnt">;
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defm UQSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b110, "uqshrnt">;
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defm UQRSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b111, "uqrshrnt">;
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// SVE2 integer add/subtract narrow high part (bottom)
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defm ADDHNB_ZZZ : sve2_int_addsub_narrow_high_bottom<0b00, "addhnb">;
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defm RADDHNB_ZZZ : sve2_int_addsub_narrow_high_bottom<0b01, "raddhnb">;
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defm SUBHNB_ZZZ : sve2_int_addsub_narrow_high_bottom<0b10, "subhnb">;
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defm RSUBHNB_ZZZ : sve2_int_addsub_narrow_high_bottom<0b11, "rsubhnb">;
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// SVE2 integer add/subtract narrow high part (top)
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defm ADDHNT_ZZZ : sve2_int_addsub_narrow_high_top<0b00, "addhnt">;
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defm RADDHNT_ZZZ : sve2_int_addsub_narrow_high_top<0b01, "raddhnt">;
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defm SUBHNT_ZZZ : sve2_int_addsub_narrow_high_top<0b10, "subhnt">;
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defm RSUBHNT_ZZZ : sve2_int_addsub_narrow_high_top<0b11, "rsubhnt">;
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// SVE2 saturating extract narrow (bottom)
|
|
defm SQXTNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b00, "sqxtnb">;
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defm UQXTNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b01, "uqxtnb">;
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defm SQXTUNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b10, "sqxtunb">;
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// SVE2 saturating extract narrow (top)
|
|
defm SQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b00, "sqxtnt">;
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defm UQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b01, "uqxtnt">;
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defm SQXTUNT_ZZ : sve2_int_sat_extract_narrow_top<0b10, "sqxtunt">;
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// SVE2 character match
|
|
defm MATCH_PPzZZ : sve2_char_match<0b0, "match">;
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defm NMATCH_PPzZZ : sve2_char_match<0b1, "nmatch">;
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// SVE2 bitwise exclusive-or interleaved
|
|
defm EORBT_ZZZ : sve2_bitwise_xor_interleaved<0b0, "eorbt">;
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defm EORTB_ZZZ : sve2_bitwise_xor_interleaved<0b1, "eortb">;
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// SVE2 bitwise shift left long
|
|
defm SSHLLB_ZZI : sve2_bitwise_shift_left_long<0b00, "sshllb">;
|
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defm SSHLLT_ZZI : sve2_bitwise_shift_left_long<0b01, "sshllt">;
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defm USHLLB_ZZI : sve2_bitwise_shift_left_long<0b10, "ushllb">;
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defm USHLLT_ZZI : sve2_bitwise_shift_left_long<0b11, "ushllt">;
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// SVE2 integer add/subtract interleaved long
|
|
defm SADDLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b00, "saddlbt">;
|
|
defm SSUBLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b10, "ssublbt">;
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defm SSUBLTB_ZZZ : sve2_misc_int_addsub_long_interleaved<0b11, "ssubltb">;
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|
// SVE2 histogram generation (segment)
|
|
def HISTSEG_ZZZ : sve2_hist_gen_segment<"histseg">;
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|
// SVE2 histogram generation (vector)
|
|
defm HISTCNT_ZPzZZ : sve2_hist_gen_vector<"histcnt">;
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// SVE2 floating-point base 2 logarithm as integer
|
|
defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">;
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|
// SVE2 floating-point convert precision
|
|
defm FCVTXNT_ZPmZ : sve2_fp_convert_down_odd_rounding<"fcvtxnt">;
|
|
defm FCVTNT_ZPmZ : sve2_fp_convert_down_narrow<"fcvtnt">;
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|
defm FCVTLT_ZPmZ : sve2_fp_convert_up_long<"fcvtlt">;
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def FCVTX_ZPmZ_DtoS : sve_fp_2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32, ElementSizeD>;
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// SVE2 floating-point pairwise operations
|
|
defm FADDP_ZPmZZ : sve2_fp_pairwise_pred<0b000, "faddp">;
|
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defm FMAXNMP_ZPmZZ : sve2_fp_pairwise_pred<0b100, "fmaxnmp">;
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defm FMINNMP_ZPmZZ : sve2_fp_pairwise_pred<0b101, "fminnmp">;
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defm FMAXP_ZPmZZ : sve2_fp_pairwise_pred<0b110, "fmaxp">;
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defm FMINP_ZPmZZ : sve2_fp_pairwise_pred<0b111, "fminp">;
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// SVE2 floating-point multiply-add long (indexed)
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def FMLALB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b00, "fmlalb">;
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def FMLALT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b01, "fmlalt">;
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def FMLSLB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b10, "fmlslb">;
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def FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt">;
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// SVE2 floating-point multiply-add long
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def FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb">;
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def FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt">;
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def FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb">;
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def FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt">;
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// SVE2 bitwise ternary operations
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defm EOR3_ZZZZ_D : sve2_int_bitwise_ternary_op<0b000, "eor3">;
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defm BCAX_ZZZZ_D : sve2_int_bitwise_ternary_op<0b010, "bcax">;
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def BSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b001, "bsl">;
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def BSL1N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b011, "bsl1n">;
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def BSL2N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b101, "bsl2n">;
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def NBSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b111, "nbsl">;
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// SVE2 bitwise xor and rotate right by immediate
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defm XAR_ZZZI : sve2_int_rotate_right_imm<"xar">;
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// SVE2 extract vector (immediate offset, constructive)
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def EXT_ZZI_B : sve2_int_perm_extract_i_cons<"ext">;
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// SVE2 non-temporal gather loads
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defm LDNT1SB_ZZR_S : sve2_mem_gldnt_vs<0b00000, "ldnt1sb", Z_s, ZPR32>;
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defm LDNT1B_ZZR_S : sve2_mem_gldnt_vs<0b00001, "ldnt1b", Z_s, ZPR32>;
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defm LDNT1SH_ZZR_S : sve2_mem_gldnt_vs<0b00100, "ldnt1sh", Z_s, ZPR32>;
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defm LDNT1H_ZZR_S : sve2_mem_gldnt_vs<0b00101, "ldnt1h", Z_s, ZPR32>;
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defm LDNT1W_ZZR_S : sve2_mem_gldnt_vs<0b01001, "ldnt1w", Z_s, ZPR32>;
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defm LDNT1SB_ZZR_D : sve2_mem_gldnt_vs<0b10000, "ldnt1sb", Z_d, ZPR64>;
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defm LDNT1B_ZZR_D : sve2_mem_gldnt_vs<0b10010, "ldnt1b", Z_d, ZPR64>;
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defm LDNT1SH_ZZR_D : sve2_mem_gldnt_vs<0b10100, "ldnt1sh", Z_d, ZPR64>;
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defm LDNT1H_ZZR_D : sve2_mem_gldnt_vs<0b10110, "ldnt1h", Z_d, ZPR64>;
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defm LDNT1SW_ZZR_D : sve2_mem_gldnt_vs<0b11000, "ldnt1sw", Z_d, ZPR64>;
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defm LDNT1W_ZZR_D : sve2_mem_gldnt_vs<0b11010, "ldnt1w", Z_d, ZPR64>;
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defm LDNT1D_ZZR_D : sve2_mem_gldnt_vs<0b11110, "ldnt1d", Z_d, ZPR64>;
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// SVE2 vector splice (constructive)
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defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice">;
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// SVE2 non-temporal scatter stores
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defm STNT1B_ZZR_S : sve2_mem_sstnt_vs<0b001, "stnt1b", Z_s, ZPR32>;
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defm STNT1H_ZZR_S : sve2_mem_sstnt_vs<0b011, "stnt1h", Z_s, ZPR32>;
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defm STNT1W_ZZR_S : sve2_mem_sstnt_vs<0b101, "stnt1w", Z_s, ZPR32>;
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defm STNT1B_ZZR_D : sve2_mem_sstnt_vs<0b000, "stnt1b", Z_d, ZPR64>;
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defm STNT1H_ZZR_D : sve2_mem_sstnt_vs<0b010, "stnt1h", Z_d, ZPR64>;
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defm STNT1W_ZZR_D : sve2_mem_sstnt_vs<0b100, "stnt1w", Z_d, ZPR64>;
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defm STNT1D_ZZR_D : sve2_mem_sstnt_vs<0b110, "stnt1d", Z_d, ZPR64>;
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// SVE2 table lookup (three sources)
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defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl">;
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defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">;
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// SVE2 integer compare scalar count and limit
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defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege">;
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defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt">;
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defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs">;
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defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi">;
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defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege">;
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defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt">;
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defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs">;
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defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi">;
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// SVE2 pointer conflict compare
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defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr">;
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defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw">;
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}
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let Predicates = [HasSVE2AES] in {
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// SVE2 crypto destructive binary operations
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def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8>;
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def AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8>;
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// SVE2 crypto unary operations
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def AESMC_ZZ_B : sve2_crypto_unary_op<0b0, "aesmc">;
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def AESIMC_ZZ_B : sve2_crypto_unary_op<0b1, "aesimc">;
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// PMULLB and PMULLT instructions which operate with 64-bit source and
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// 128-bit destination elements are enabled with crypto extensions, similar
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// to NEON PMULL2 instruction.
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def PMULLB_ZZZ_Q : sve2_wide_int_arith<0b00, 0b11010, "pmullb",
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ZPR128, ZPR64, ZPR64>;
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def PMULLT_ZZZ_Q : sve2_wide_int_arith<0b00, 0b11011, "pmullt",
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ZPR128, ZPR64, ZPR64>;
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}
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let Predicates = [HasSVE2SM4] in {
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// SVE2 crypto constructive binary operations
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def SM4EKEY_ZZZ_S : sve2_crypto_cons_bin_op<0b0, "sm4ekey", ZPR32>;
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// SVE2 crypto destructive binary operations
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def SM4E_ZZZ_S : sve2_crypto_des_bin_op<0b10, "sm4e", ZPR32>;
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}
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let Predicates = [HasSVE2SHA3] in {
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// SVE2 crypto constructive binary operations
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def RAX1_ZZZ_D : sve2_crypto_cons_bin_op<0b1, "rax1", ZPR64>;
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}
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let Predicates = [HasSVE2BitPerm] in {
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// SVE2 bitwise permute
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defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext">;
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defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep">;
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defm BGRP_ZZZ : sve2_misc_bitwise<0b1110, "bgrp">;
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}
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