llvm-project/llvm/test/CodeGen
Thomas Lively f6f4f84378 [WebAssembly] Target features section
Summary:
Implements a new target features section in assembly and object files
that records what features are used, required, and disallowed in
WebAssembly objects. The linker uses this information to ensure that
all objects participating in a link are feature-compatible and records
the set of used features in the output binary for use by optimizers
and other tools later in the toolchain.

The "atomics" feature is always required or disallowed to prevent
linking code with stripped atomics into multithreaded binaries. Other
features are marked used if they are enabled globally or on any
function in a module.

Future CLs will add linker flags for ignoring feature compatibility
checks and for specifying the set of allowed features, implement using
the presence of the "atomics" feature to control the type of memory
and segments in the linked binary, and add front-end flags for
relaxing the linkage policy for atomics.

Reviewers: aheejin, sbc100, dschuff

Subscribers: jgravelle-google, hiraditya, sunfish, mgrang, jfb, jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59173

llvm-svn: 356610
2019-03-20 20:26:45 +00:00
..
AArch64 [AArch64][GlobalISel] Add an optimization to select vector DUP instructions. 2019-03-19 21:43:05 +00:00
AMDGPU [AMDGPU] Fix clamp bit DAG operand 2019-03-20 20:18:56 +00:00
ARC [ARC] Add ARCOptAddrMode pass to generate postincrement loads/stores. 2019-03-20 20:06:21 +00:00
ARM [ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1. 2019-03-20 19:40:45 +00:00
AVR [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later. 2019-03-13 17:07:09 +00:00
BPF [BPF] Add BTF Var and DataSec Support 2019-03-16 15:36:31 +00:00
Generic [AVR] Remove unneeded XFAILs from the Generic CodeGen tests 2019-01-20 11:16:58 +00:00
Hexagon [Hexagon] Remove icmp undef from reduced tests 2019-03-15 15:07:44 +00:00
Inputs
Lanai
MIR MIR: Allow targets to serialize MachineFunctionInfo 2019-03-14 22:54:43 +00:00
MSP430 [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later. 2019-03-13 17:07:09 +00:00
Mips RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs 2019-03-19 19:01:34 +00:00
NVPTX [Codegen] fix typos in test case 2019-03-02 08:03:59 +00:00
PowerPC RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs 2019-03-19 19:01:34 +00:00
RISCV [RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs 2019-03-14 08:17:44 +00:00
SPARC [SPARC] Regenerate label test for D59363 2019-03-15 11:24:17 +00:00
SystemZ RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs 2019-03-19 19:01:34 +00:00
Thumb [ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1. 2019-03-20 19:40:45 +00:00
Thumb2 [ARM] Check that CPSR does not have other uses 2019-03-17 21:36:15 +00:00
WebAssembly [WebAssembly] Target features section 2019-03-20 20:26:45 +00:00
WinCFGuard
WinEH Fix invalid target triples in tests. (NFC) 2019-03-04 23:37:41 +00:00
X86 [CGP][x86] add tests for usubo regression (PR41129); NFC 2019-03-20 15:02:35 +00:00
XCore [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later. 2019-03-13 17:07:09 +00:00