forked from OSchip/llvm-project
111 lines
3.4 KiB
Plaintext
111 lines
3.4 KiB
Plaintext
{
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"arrays" : [
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{
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"name" : "MemRef_C",
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"sizes" : [ "*", "1024" ],
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"type" : "float"
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},
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{
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"name" : "MemRef_A",
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"sizes" : [ "*", "1024" ],
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"type" : "float"
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},
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{
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"name" : "MemRef_B",
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"sizes" : [ "*", "1024" ],
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"type" : "float"
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}
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],
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"context" : "{ : }",
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"name" : "%bb3---%bb28",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb8[i0, i1] -> MemRef_C[i0, i1] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb8[i0, i1] -> MemRef_tmp_0__phi[] }"
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}
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],
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"domain" : "{ Stmt_bb8[i0, i1] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 }",
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"name" : "Stmt_bb8",
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"schedule" : "{ Stmt_bb8[i0, i1] -> [i0, i1, 0, 0, 0] }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb10[i0, i1, i2] -> MemRef_tmp_0__phi[] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb10[i0, i1, i2] -> MemRef_tmp_0[] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb10[i0, i1, i2] -> MemRef_tmp_0_lcssa__phi[] }"
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}
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],
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"domain" : "{ Stmt_bb10[i0, i1, i2] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 and 0 <= i2 <= 1024 }",
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"name" : "Stmt_bb10",
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"schedule" : "{ Stmt_bb10[i0, i1, i2] -> [i0, i1, 1, i2, 0] }"
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},
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb13[i0, i1, i2] -> MemRef_tmp_0__phi[] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb13[i0, i1, i2] -> MemRef_A[i0, i2] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb13[i0, i1, i2] -> MemRef_B[i2, i1] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb13[i0, i1, i2] -> MemRef_tmp_0[] }"
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}
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],
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"domain" : "{ Stmt_bb13[i0, i1, i2] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 and 0 <= i2 <= 1023 }",
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"name" : "Stmt_bb13",
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"schedule" : "{ Stmt_bb13[i0, i1, i2] -> [i0, i1, 1, i2, 1] }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb11[i0, i1] -> MemRef_tmp_0_lcssa__phi[] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb11[i0, i1] -> MemRef_tmp_0_lcssa[] }"
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}
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],
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"domain" : "{ Stmt_bb11[i0, i1] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 }",
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"name" : "Stmt_bb11",
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"schedule" : "{ Stmt_bb11[i0, i1] -> [i0, i1, 2, 0, 0] }"
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},
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb21[i0, i1] -> MemRef_C[i0, i1] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb21[i0, i1] -> MemRef_tmp_0_lcssa[] }"
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}
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],
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"domain" : "{ Stmt_bb21[i0, i1] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 }",
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"name" : "Stmt_bb21",
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"schedule" : "{ Stmt_bb21[i0, i1] -> [i0, i1, 3, 0, 0] }"
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}
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]
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}
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