forked from OSchip/llvm-project
72 lines
2.8 KiB
LLVM
72 lines
2.8 KiB
LLVM
; RUN: opt %loadPolly -polly-delicm -analyze < %s | FileCheck %s
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; When %b is 0, %for.body13 is an infite loop. In this case the loaded
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; value %1 is not used anywhere.
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; This is a problem when DeLICM tries to map %1 to %arrayidx16 because
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; %1 has no corresponding when %b == 0 and therefore hat no location
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; where it can be mapped to. However, since %b == 0 results in an
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; infinite loop, it should not in the Context, or in this case, in the
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; InvalidContext.
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;
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; Test case reduced from llvm.org/PR48445.
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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@arr_18 = external dso_local local_unnamed_addr global [0 x i16], align 2
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define void @func(i64 %b, i8* %c) {
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entry:
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%conv1 = trunc i64 %b to i32
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%sext = shl i32 %conv1, 24
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%conv2 = ashr exact i32 %sext, 24
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%arrayidx = getelementptr inbounds i8, i8* %c, i64 %b
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%tobool19.not = icmp eq i64 %b, 0
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br label %for.cond3.preheader
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for.cond3.preheader:
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%d.039 = phi i16 [ 0, %entry ], [ %inc, %for.cond.cleanup6 ]
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%idxprom = sext i16 %d.039 to i64
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br label %for.cond8.preheader
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for.cond8.preheader:
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br label %for.body13
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for.cond.cleanup6:
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%arrayidx16 = getelementptr inbounds [0 x i16], [0 x i16]* @arr_18, i64 0, i64 %idxprom
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%0 = zext i8 %1 to i16
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store i16 %0, i16* %arrayidx16, align 2
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%inc = add i16 %d.039, 1
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%conv = sext i16 %inc to i32
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%cmp = icmp sgt i32 %conv2, %conv
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br i1 %cmp, label %for.cond3.preheader, label %for.cond.cleanup
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for.cond.cleanup12:
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br i1 false, label %for.cond8.preheader, label %for.cond.cleanup6
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for.body13:
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%1 = load i8, i8* %arrayidx, align 1
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br i1 %tobool19.not, label %for.body13, label %for.cond.cleanup12
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for.cond.cleanup:
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ret void
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}
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; CHECK: Statistics {
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; CHECK: Value scalars mapped: 1
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; CHECK: }
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; CHECK: After accesses {
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; CHECK-NEXT: Stmt_for_body13
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [b] -> { Stmt_for_body13[i0, i1, i2] -> MemRef_c[b] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [b] -> { Stmt_for_body13[i0, i1, i2] -> MemRef1[] };
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; CHECK-NEXT: new: [b] -> { Stmt_for_body13[i0, i1, i2] -> MemRef_arr_18[i0] : i0 < b; Stmt_for_body13[0, i1, i2] -> MemRef_arr_18[0] : b < 0 };
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; CHECK-NEXT: Stmt_for_cond_cleanup6
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [b] -> { Stmt_for_cond_cleanup6[i0] -> MemRef1[] };
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; CHECK-NEXT: new: [b] -> { Stmt_for_cond_cleanup6[i0] -> MemRef_arr_18[i0] : i0 < b; Stmt_for_cond_cleanup6[0] -> MemRef_arr_18[0] : b < 0 };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [b] -> { Stmt_for_cond_cleanup6[i0] -> MemRef_arr_18[i0] };
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; CHECK-NEXT: }
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