llvm-project/polly/test/DeLICM/confused_order___%for.end10...

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{
"arrays" : [
{
"name" : "MemRef_C",
"sizes" : [ "*" ],
"type" : "double"
}
],
"context" : "[cols, rows] -> { : -2147483648 <= cols <= 2147483647 and -2147483648 <= rows <= 2147483647 }",
"name" : "%for.end103---%for.inc116",
"statements" : [
{
"accesses" : [
{
"kind" : "read",
"relation" : "[cols, rows] -> { Stmt_for_end103[] -> MemRef_a_dot_b_domain_0_lcssa__phi[] }"
},
{
"kind" : "write",
"relation" : "[cols, rows] -> { Stmt_for_end103[] -> MemRef_C[0] }"
},
{
"kind" : "write",
"relation" : "[cols, rows] -> { Stmt_for_end103[] -> MemRef_a_dot_b_domain_0_lcssa[] }"
}
],
"domain" : "[cols, rows] -> { Stmt_for_end103[] }",
"name" : "Stmt_for_end103",
"schedule" : "[cols, rows] -> { Stmt_for_end103[] -> [0] }"
},
{
"accesses" : [
{
"kind" : "write",
"relation" : "[cols, rows] -> { Stmt_if_then110[] -> MemRef_C[0] }"
},
{
"kind" : "read",
"relation" : "[cols, rows] -> { Stmt_if_then110[] -> MemRef_a_dot_b_domain_0_lcssa[] }"
}
],
"domain" : "[cols, rows] -> { Stmt_if_then110[] : cols > 0 and rows > 0 }",
"name" : "Stmt_if_then110",
"schedule" : "[cols, rows] -> { Stmt_if_then110[] -> [1] }"
}
]
}