..
AsmParser
[AMDGPU][MC] Improved diagnostic messages
2020-11-23 16:15:05 +03:00
Disassembler
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
MCTargetDesc
[AsmWriter] Factor out mnemonic generation to accessible getMnemonic.
2020-11-17 09:47:38 +00:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Utils
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
AMDGPU.h
[amdgpu] Add the late codegen preparation pass.
2020-10-27 14:07:59 -04:00
AMDGPU.td
Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
2020-11-11 14:40:14 +00:00
AMDGPUAliasAnalysis.cpp
[amdgpu] Enhance AMDGPU AA.
2020-10-20 09:54:12 -04:00
AMDGPUAliasAnalysis.h
Remove orphan AMDGPUAAResult::Aliases and AMDGPUAAResult::PathAliases declarations. NFC.
2020-06-25 16:00:44 +01:00
AMDGPUAlwaysInlinePass.cpp
AMDGPU: Hack out noinline on functions using LDS globals
2020-04-02 14:12:07 -04:00
AMDGPUAnnotateKernelFeatures.cpp
AMDGPU: Annotate functions that have stack objects
2020-05-19 18:51:00 -04:00
AMDGPUAnnotateUniformValues.cpp
[MemLoc] Require LocationSize argument (NFC)
2020-11-19 21:45:52 +01:00
AMDGPUArgumentUsageInfo.cpp
AMDGPU/GlobalISel: Add types to special inputs
2020-07-06 17:00:55 -04:00
AMDGPUArgumentUsageInfo.h
AMDGPU: Use MCRegister for preloaded arguments
2020-07-20 13:34:28 -04:00
AMDGPUAsmPrinter.cpp
AMDGPU: Fix counting kernel arguments towards register usage
2020-11-20 21:23:33 -05:00
AMDGPUAsmPrinter.h
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
2020-02-13 22:08:55 -08:00
AMDGPUAtomicOptimizer.cpp
[AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer
2020-09-30 11:09:18 +02:00
AMDGPUCallLowering.cpp
[AMDGPU] Omit buffer resource with flat scratch.
2020-11-09 08:05:20 -08:00
AMDGPUCallLowering.h
AMDGPU/GlobalISel: Mark GlobalISel classes as final
2020-07-28 11:42:17 -04:00
AMDGPUCallingConv.td
[AMDGPU] Add amdgpu_gfx calling convention
2020-11-09 16:51:44 +01:00
AMDGPUCodeGenPrepare.cpp
SelectionDAG.h - remove unnecessary FunctionLoweringInfo.h include. NFCI.
2020-09-03 18:33:25 +01:00
AMDGPUCombine.td
AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combiner
2020-11-03 09:24:50 +01:00
AMDGPUExportClustering.cpp
[AMDGPU] Fix scheduling of exp pos4
2020-11-12 19:57:14 +00:00
AMDGPUExportClustering.h
[AMDGPU] Cluster shader exports
2020-05-07 19:05:38 +09:00
AMDGPUFeatures.td
AMDGPU: Change internal tracking of wave size
2020-06-01 17:55:08 -04:00
AMDGPUFixFunctionBitcasts.cpp
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
[Alignment][NFC] Deprecate Align::None()
2020-01-24 12:53:58 +01:00
AMDGPUGISel.td
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
2020-08-21 12:26:31 +02:00
AMDGPUGenRegisterBankInfo.def
AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping
2020-08-17 09:53:26 -04:00
AMDGPUGlobalISelUtils.cpp
[AMDGPU] Remove an unused return value. NFC.
2020-11-10 09:15:14 +00:00
AMDGPUGlobalISelUtils.h
[AMDGPU] Remove an unused return value. NFC.
2020-11-10 09:15:14 +00:00
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Start interpreting byref on kernel arguments
2020-07-21 18:11:22 -04:00
AMDGPUHSAMetadataStreamer.h
AMDGPU: Start interpreting byref on kernel arguments
2020-07-21 18:11:22 -04:00
AMDGPUISelDAGToDAG.cpp
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
AMDGPUISelLowering.cpp
[AMDGPU] Add amdgpu_gfx calling convention
2020-11-09 16:51:44 +01:00
AMDGPUISelLowering.h
[AMDGPU] Some refactoring after D90404. NFC.
2020-11-01 13:18:53 +05:30
AMDGPUInline.cpp
[NFC] Remove unused GetUnderlyingObject paramenter
2020-07-31 02:10:03 -07:00
AMDGPUInstCombineIntrinsic.cpp
[AMDGPU] Add simplification/combines for llvm.amdgcn.fma.legacy
2020-10-23 16:16:13 +01:00
AMDGPUInstrInfo.cpp
[AMDGPU] Remove AMDGPURegisterInfo
2020-02-11 11:13:38 -08:00
AMDGPUInstrInfo.h
[AMDGPU] Use tablegen for argument indices
2020-10-05 11:50:52 +02:00
AMDGPUInstrInfo.td
AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
2020-06-16 21:06:25 -04:00
AMDGPUInstructionSelector.cpp
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
AMDGPUInstructionSelector.h
AMDGPU: Split large offsets when selecting global saddr mode
2020-11-16 11:36:01 -05:00
AMDGPUInstructions.td
[TableGen] Add the !filter bang operator.
2020-11-09 10:56:55 -05:00
AMDGPULateCodeGenPrepare.cpp
[amdgpu] Add the late codegen preparation pass.
2020-10-27 14:07:59 -04:00
AMDGPULegalizerInfo.cpp
[AMDGPU] Fix v3f16 interaction with image store workaround
2020-11-18 18:21:04 +01:00
AMDGPULegalizerInfo.h
[AMDGPU] Implement hardware bug workaround for image instructions
2020-10-07 07:39:52 -04:00
AMDGPULibCalls.cpp
[AMDGPU] Mark sin/cos load folding as modifying the function.
2020-11-13 14:49:33 -08:00
AMDGPULibFunc.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPULibFunc.h
AMDGPULibFunc - fix include order. NFC.
2020-05-24 13:25:59 +01:00
AMDGPULowerIntrinsics.cpp
AMDGPU: Use caller subtarget, not intrinsic declaration
2020-08-27 16:42:09 -04:00
AMDGPULowerKernelArguments.cpp
AMDGPU: Start interpreting byref on kernel arguments
2020-07-21 18:11:22 -04:00
AMDGPULowerKernelAttributes.cpp
…
AMDGPUMCInstLower.cpp
AMDGPU: Increase branch size estimate with offset bug
2020-10-23 10:34:24 -04:00
AMDGPUMachineCFGStructurizer.cpp
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
2020-08-21 10:14:35 +01:00
AMDGPUMachineFunction.cpp
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
AMDGPUMachineFunction.h
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
AMDGPUMachineModuleInfo.cpp
…
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
2020-03-11 17:59:21 +00:00
AMDGPUMacroFusion.h
…
AMDGPUOpenCLEnqueuedBlockLowering.cpp
Avoid SmallString.h include in MD5.h, NFC
2020-02-26 09:10:24 -08:00
AMDGPUPTNote.h
…
AMDGPUPerfHintAnalysis.cpp
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPUPerfHintAnalysis.h
…
AMDGPUPostLegalizerCombiner.cpp
AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combiner
2020-11-03 09:24:50 +01:00
AMDGPUPreLegalizerCombiner.cpp
AMDGPU/GlobalISel: Mark GlobalISel classes as final
2020-07-28 11:42:17 -04:00
AMDGPUPrintfRuntimeBinding.cpp
AMDGPUPrintfRuntimeBinding.cpp - drop unnecessary casts/dyn_casts. NFCI.
2020-09-15 14:49:04 +01:00
AMDGPUPromoteAlloca.cpp
[NFC] Remove unused GetUnderlyingObject paramenter
2020-07-31 02:10:03 -07:00
AMDGPUPropagateAttributes.cpp
AMDGPU: Propagate amdgpu-flat-work-group-size attributes
2020-10-21 12:06:24 -04:00
AMDGPURegBankCombiner.cpp
AMDGPU/GlobalISel: Mark GlobalISel classes as final
2020-07-28 11:42:17 -04:00
AMDGPURegisterBankInfo.cpp
[AMDGPU] Remove an unused return value. NFC.
2020-11-10 09:15:14 +00:00
AMDGPURegisterBankInfo.h
AMDGPU/GlobalISel: Start trying to handle AGPR bank
2020-08-06 12:39:50 -04:00
AMDGPURegisterBanks.td
AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank
2020-07-28 16:49:55 -04:00
AMDGPURewriteOutArguments.cpp
[MemLoc] Require LocationSize argument (NFC)
2020-11-19 21:45:52 +01:00
AMDGPUSearchableTables.td
AMDGPU: Define raw/struct variants of buffer atomic fadd
2020-08-06 13:36:19 -04:00
AMDGPUSubtarget.cpp
Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
2020-11-11 14:40:14 +00:00
AMDGPUSubtarget.h
[AMDGPU] Enable multi-dword flat scratch load/stores
2020-11-12 13:38:56 -08:00
AMDGPUTargetMachine.cpp
[AMDGPU] Set the default globals address space to 1
2020-11-20 15:46:53 +00:00
AMDGPUTargetMachine.h
[InferAddrSpace] Teach to handle assumed address space.
2020-11-16 17:06:33 -05:00
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
AMDGPUTargetObjectFile.h - remove unnecessary includes. NFC.
2020-05-24 13:57:02 +01:00
AMDGPUTargetTransformInfo.cpp
[AMDGPU] Add amdgpu_gfx calling convention
2020-11-09 16:51:44 +01:00
AMDGPUTargetTransformInfo.h
Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
2020-11-11 14:40:14 +00:00
AMDGPUUnifyDivergentExitNodes.cpp
[AMDGPU] One more use of the new export target names. NFC.
2020-11-13 09:44:09 +00:00
AMDGPUUnifyMetadata.cpp
Use llvm::is_contained where appropriate (NFC)
2020-07-27 10:20:44 -07:00
AMDILCFGStructurizer.cpp
…
AMDKernelCodeT.h
…
BUFInstructions.td
[AMDGPU] Add default 1 glc operand to rtn atomics
2020-11-05 10:41:59 -08:00
CMakeLists.txt
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
CaymanInstructions.td
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
DSInstructions.td
[AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds
2020-10-29 17:31:59 +00:00
EXPInstructions.td
[AMDGPU] Separate out real exp instructions by subtarget. NFC.
2020-11-11 17:13:40 +00:00
EvergreenInstructions.td
[AMDGPU] Omit needless string concatenations. NFC.
2020-10-28 12:56:52 +00:00
FLATInstructions.td
[AMDGPU] Add default 1 glc operand to rtn atomics
2020-11-05 10:41:59 -08:00
GCNDPPCombine.cpp
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
GCNHazardRecognizer.cpp
[AMDGPU] Rename pseudo S_WAITCNT_IDLE to S_WAIT_IDLE. NFC.
2020-11-18 14:03:43 +00:00
GCNHazardRecognizer.h
[AMDGPU] Add Reset function to GCNHazardRecognizer
2020-10-28 16:32:32 -07:00
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[AMDGPU] Add file headers for few files where it is missing.
2020-01-31 02:06:41 +05:30
GCNIterativeScheduler.h
[AMDGPU] Add file headers for few files where it is missing.
2020-01-31 02:06:41 +05:30
GCNMinRegStrategy.cpp
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
2020-09-21 13:33:05 +02:00
GCNNSAReassign.cpp
[NFC][MC] Use MCRegister in LiveRangeMatrix
2020-10-12 08:54:36 -07:00
GCNProcessors.td
[AMDGPU] Add gfx1033 target
2020-11-03 16:27:48 +00:00
GCNRegBankReassign.cpp
[AMDGPU] Resolve pseudo registers at encoding uses
2020-11-04 12:52:32 -05:00
GCNRegPressure.cpp
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
2020-08-20 17:59:11 +01:00
GCNRegPressure.h
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
2020-08-20 17:59:11 +01:00
GCNSchedStrategy.cpp
[AMDGPU] Fix not rescheduling without clustering
2020-08-07 11:15:58 -07:00
GCNSchedStrategy.h
[AMDGPU] Attempt to reschedule withou clustering
2020-01-27 10:27:16 -08:00
InstCombineTables.td
[InstCombine] Move target-specific inst combining
2020-07-22 15:59:49 +02:00
MIMGInstructions.td
[TableGen] Add the !filter bang operator.
2020-11-09 10:56:55 -05:00
R600.td
…
R600AsmPrinter.cpp
[MC] Add MCStreamer::emitInt{8,16,32,64}
2020-02-29 09:40:21 -08:00
R600AsmPrinter.h
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
2020-02-13 22:08:55 -08:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
[AMDGPU] Make use of divideCeil. NFC.
2020-03-26 16:11:35 +00:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
[AMDGPU] Split R600 and GCN subregs
2020-02-10 08:29:56 -08:00
R600FrameLowering.cpp
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
R600FrameLowering.h
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
R600ISelLowering.cpp
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
R600ISelLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
R600InstrInfo.h
Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate
2020-10-21 11:52:47 +01:00
R600Instructions.td
[NFC] Remove unused GetUnderlyingObject paramenter
2020-07-31 02:10:03 -07:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
2020-08-20 17:59:11 +01:00
R600MachineScheduler.h
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
2020-08-20 17:59:11 +01:00
R600OpenCLImageTypeLoweringPass.cpp
…
R600OptimizeVectorRegisters.cpp
AMDGPU: Use Register
2020-06-30 12:13:08 -04:00
R600Packetizer.cpp
…
R600Processors.td
…
R600RegisterInfo.cpp
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
2020-08-20 17:59:11 +01:00
R600RegisterInfo.h
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
2020-08-20 17:59:11 +01:00
R600RegisterInfo.td
[TBLGEN] Allow to override RC weight
2020-02-14 15:49:52 -08:00
R600Schedule.td
…
R700Instructions.td
…
SIAddIMGInit.cpp
[AMDGPU] gfx1030 RT support
2020-09-16 11:40:58 -07:00
SIAnnotateControlFlow.cpp
AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break
2020-02-03 07:02:05 -08:00
SIDefines.h
[AMDGPU] Add a TRANS bit to TSFlags. NFC.
2020-11-24 17:49:56 +00:00
SIFixSGPRCopies.cpp
[AMDGPU] Fix iterating in SIFixSGPRCopies
2020-11-04 18:43:19 +01:00
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
[AMDGPU] Use flat scratch instructions where available
2020-10-26 14:40:42 -07:00
SIFormMemoryClauses.cpp
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
2020-08-20 17:59:11 +01:00
SIFrameLowering.cpp
[AMDGPU] Implement flat scratch init for pal
2020-11-20 11:14:30 +01:00
SIFrameLowering.h
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
SIISelLowering.cpp
[AMDGPU] Implement flat scratch init for pal
2020-11-20 11:14:30 +01:00
SIISelLowering.h
[AMDGPU] Implement hardware bug workaround for image instructions
2020-10-07 07:39:52 -04:00
SIInsertHardClauses.cpp
[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
2020-06-01 22:52:34 +05:30
SIInsertSkips.cpp
[AMDGPU] Define and use names for export targets. NFC.
2020-11-12 19:57:14 +00:00
SIInsertWaitcnts.cpp
[AMDGPU] Fix and extend vccz workarounds
2020-11-18 15:26:06 +00:00
SIInstrFormats.td
[AMDGPU] Add a TRANS bit to TSFlags. NFC.
2020-11-24 17:49:56 +00:00
SIInstrInfo.cpp
AMDGPU: Factor out large flat offset splitting
2020-11-13 11:22:13 -05:00
SIInstrInfo.h
[AMDGPU] Add a TRANS bit to TSFlags. NFC.
2020-11-24 17:49:56 +00:00
SIInstrInfo.td
[AMDGPU] Split exp instructions out into their own tablegen file. NFC.
2020-11-11 17:13:40 +00:00
SIInstructions.td
[AMDGPU] Remove scratch rsrc from spill pseudos
2020-11-12 15:23:37 -08:00
SILoadStoreOptimizer.cpp
[AMDGPU] gfx1030 RT support
2020-09-16 11:40:58 -07:00
SILowerControlFlow.cpp
[AMDGPU] SILowerControlFlow::removeMBBifRedundant. Refactoring plus fix for the null MBB pointer in MF->splice
2020-10-30 14:46:08 +03:00
SILowerI1Copies.cpp
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
2020-08-21 10:14:35 +01:00
SILowerSGPRSpills.cpp
[AMDGPU] Add amdgpu_gfx calling convention
2020-11-09 16:51:44 +01:00
SIMachineFunctionInfo.cpp
[AMDGPU] Omit buffer resource with flat scratch.
2020-11-09 08:05:20 -08:00
SIMachineFunctionInfo.h
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
SIMachineScheduler.cpp
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
2020-08-20 17:59:11 +01:00
SIMachineScheduler.h
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
2020-09-21 13:33:05 +02:00
SIMemoryLegalizer.cpp
[NFC][AMDGPU] Reorder SIMemoryLegalizer functions to be consistent
2020-10-22 05:39:18 +00:00
SIModeRegister.cpp
[AMDGPU] Enable scheduling around FP MODE-setting instructions
2020-09-16 16:10:47 +01:00
SIOptimizeExecMasking.cpp
[AMDGPU] Fix lowering of S_MOV_{B32,B64}_term
2020-11-10 12:16:31 +09:00
SIOptimizeExecMaskingPreRA.cpp
[NFC] Use Register/MCRegister
2020-11-04 12:20:17 -08:00
SIPeepholeSDWA.cpp
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
2020-08-20 17:59:11 +01:00
SIPostRABundler.cpp
AMDGPU: Do not bundle inline asm
2020-06-14 13:24:50 -04:00
SIPreAllocateWWMRegs.cpp
AMDGPU: Reorder checks
2020-11-02 10:21:48 -05:00
SIPreEmitPeephole.cpp
[AMDGPU] Fix missed SI_RETURN_TO_EPILOG in pre-emit peephole
2020-08-13 21:52:41 +09:00
SIProgramInfo.cpp
[AMDGPU] Set rsrc1 flags for graphics shaders
2020-11-04 12:25:41 +01:00
SIProgramInfo.h
[AMDGPU] Set rsrc1 flags for graphics shaders
2020-11-04 12:25:41 +01:00
SIRegisterInfo.cpp
[AMDGPU] Implement flat scratch init for pal
2020-11-20 11:14:30 +01:00
SIRegisterInfo.h
[AMDGPU] Implement flat scratch init for pal
2020-11-20 11:14:30 +01:00
SIRegisterInfo.td
[TableGen] Add the !filter bang operator.
2020-11-09 10:56:55 -05:00
SIRemoveShortExecBranches.cpp
[AMDGPU] Don't remove short branches over kills
2020-02-03 09:26:52 +00:00
SISchedule.td
[AMDGPU] Add XDL resource to scheduling model
2020-09-14 13:48:54 -07:00
SIShrinkInstructions.cpp
[AMDGPU] Fix VC warning about singed/unsigned comparison. NFC.
2020-10-26 11:55:57 -07:00
SIWholeQuadMode.cpp
[NFC] Use [MC]Register
2020-11-09 08:37:14 -08:00
SMInstructions.td
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
SOPInstructions.td
[AMDGPU] Rename pseudo S_WAITCNT_IDLE to S_WAIT_IDLE. NFC.
2020-11-18 14:03:43 +00:00
VIInstrFormats.td
…
VOP1Instructions.td
[AMDGPU] Add a TRANS bit to TSFlags. NFC.
2020-11-24 17:49:56 +00:00
VOP2Instructions.td
[AMDGPU] Fix double space in disassembly of SDWA instructions with vcc
2020-10-28 21:39:39 +00:00
VOP3Instructions.td
[AMDGPU] Allow some modifiers on VOP3B instructions
2020-10-28 21:54:14 +00:00
VOP3PInstructions.td
[AMDGPU] Set default op_sel_hi on accvgpr read/write
2020-11-10 13:07:29 -08:00
VOPCInstructions.td
[AMDGPU] Corrected declaration of VOPC instructions with SDWA addressing mode.
2020-11-05 11:15:50 -05:00
VOPInstructions.td
[AMDGPU] Add a TRANS bit to TSFlags. NFC.
2020-11-24 17:49:56 +00:00
4926eed59c