forked from OSchip/llvm-project
855 lines
27 KiB
C++
855 lines
27 KiB
C++
//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetAsmParser.h"
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#include "X86.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetAsmParser.h"
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using namespace llvm;
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namespace {
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struct X86Operand;
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class X86ATTAsmParser : public TargetAsmParser {
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MCAsmParser &Parser;
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protected:
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unsigned Is64Bit : 1;
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private:
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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X86Operand *ParseOperand();
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X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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void InstructionCleanup(MCInst &Inst);
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/// @name Auto-generated Match Functions
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/// {
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bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCInst &Inst);
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bool MatchInstructionImpl(
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCInst &Inst);
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/// }
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public:
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X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
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: TargetAsmParser(T), Parser(_Parser) {}
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virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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};
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class X86_32ATTAsmParser : public X86ATTAsmParser {
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public:
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X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser)
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: X86ATTAsmParser(T, _Parser) {
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Is64Bit = false;
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}
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};
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class X86_64ATTAsmParser : public X86ATTAsmParser {
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public:
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X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser)
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: X86ATTAsmParser(T, _Parser) {
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Is64Bit = true;
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}
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};
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} // end anonymous namespace
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/// @name Auto-generated Match Functions
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/// {
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static unsigned MatchRegisterName(StringRef Name);
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/// }
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namespace {
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/// X86Operand - Instances of this class represent a parsed X86 machine
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/// instruction.
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struct X86Operand : public MCParsedAsmOperand {
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enum KindTy {
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Token,
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Register,
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Immediate,
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Memory
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} Kind;
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SMLoc StartLoc, EndLoc;
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union {
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struct {
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const char *Data;
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unsigned Length;
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} Tok;
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struct {
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unsigned RegNo;
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} Reg;
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struct {
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const MCExpr *Val;
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} Imm;
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struct {
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unsigned SegReg;
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const MCExpr *Disp;
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unsigned BaseReg;
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unsigned IndexReg;
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unsigned Scale;
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} Mem;
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};
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X86Operand(KindTy K, SMLoc Start, SMLoc End)
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: Kind(K), StartLoc(Start), EndLoc(End) {}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const { return EndLoc; }
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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void setTokenValue(StringRef Value) {
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assert(Kind == Token && "Invalid access!");
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Tok.Data = Value.data();
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Tok.Length = Value.size();
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}
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unsigned getReg() const {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNo;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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const MCExpr *getMemDisp() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Disp;
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}
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unsigned getMemSegReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.SegReg;
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}
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unsigned getMemBaseReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.BaseReg;
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}
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unsigned getMemIndexReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.IndexReg;
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}
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unsigned getMemScale() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Scale;
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}
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bool isToken() const {return Kind == Token; }
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bool isImm() const { return Kind == Immediate; }
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bool isImmSExti16i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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uint64_t Value = CE->getValue();
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return (( Value <= 0x000000000000007FULL)||
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(0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
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(0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
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}
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bool isImmSExti32i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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uint64_t Value = CE->getValue();
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return (( Value <= 0x000000000000007FULL)||
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(0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
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(0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
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}
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bool isImmSExti64i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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uint64_t Value = CE->getValue();
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return (( Value <= 0x000000000000007FULL)||
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(0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
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}
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bool isImmSExti64i32() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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uint64_t Value = CE->getValue();
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return (( Value <= 0x000000007FFFFFFFULL)||
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(0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
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}
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bool isMem() const { return Kind == Memory; }
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bool isAbsMem() const {
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return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
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!getMemIndexReg() && getMemScale() == 1;
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}
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bool isNoSegMem() const {
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return Kind == Memory && !getMemSegReg();
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}
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bool isReg() const { return Kind == Register; }
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediates when possible.
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::CreateExpr(Expr));
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}
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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}
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void addMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 5) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
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Inst.addOperand(MCOperand::CreateImm(getMemScale()));
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Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
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addExpr(Inst, getMemDisp());
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Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
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}
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void addAbsMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 1) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
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}
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void addNoSegMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 4) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
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Inst.addOperand(MCOperand::CreateImm(getMemScale()));
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Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
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addExpr(Inst, getMemDisp());
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}
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static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
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X86Operand *Res = new X86Operand(Token, Loc, Loc);
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Res->Tok.Data = Str.data();
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Res->Tok.Length = Str.size();
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return Res;
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}
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static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
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X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
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Res->Reg.RegNo = RegNo;
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return Res;
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}
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static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
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X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
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Res->Imm.Val = Val;
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return Res;
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}
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/// Create an absolute memory operand.
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static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
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SMLoc EndLoc) {
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X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
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Res->Mem.SegReg = 0;
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Res->Mem.Disp = Disp;
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Res->Mem.BaseReg = 0;
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Res->Mem.IndexReg = 0;
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Res->Mem.Scale = 1;
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return Res;
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}
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/// Create a generalized memory operand.
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static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
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unsigned BaseReg, unsigned IndexReg,
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unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
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// We should never just have a displacement, that should be parsed as an
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// absolute memory operand.
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assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
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// The scale should always be one of {1,2,4,8}.
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assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
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"Invalid scale!");
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X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
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Res->Mem.SegReg = SegReg;
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Res->Mem.Disp = Disp;
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Res->Mem.BaseReg = BaseReg;
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Res->Mem.IndexReg = IndexReg;
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Res->Mem.Scale = Scale;
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return Res;
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}
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};
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} // end anonymous namespace.
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bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
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SMLoc &StartLoc, SMLoc &EndLoc) {
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RegNo = 0;
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const AsmToken &TokPercent = Parser.getTok();
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assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
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StartLoc = TokPercent.getLoc();
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Parser.Lex(); // Eat percent token.
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const AsmToken &Tok = Parser.getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return Error(Tok.getLoc(), "invalid register name");
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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RegNo = MatchRegisterName(Tok.getString());
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// Parse %st(1) and "%st" as "%st(0)"
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if (RegNo == 0 && Tok.getString() == "st") {
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RegNo = X86::ST0;
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EndLoc = Tok.getLoc();
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Parser.Lex(); // Eat 'st'
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// Check to see if we have '(4)' after %st.
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if (getLexer().isNot(AsmToken::LParen))
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return false;
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// Lex the paren.
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getParser().Lex();
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const AsmToken &IntTok = Parser.getTok();
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if (IntTok.isNot(AsmToken::Integer))
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return Error(IntTok.getLoc(), "expected stack index");
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switch (IntTok.getIntVal()) {
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case 0: RegNo = X86::ST0; break;
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case 1: RegNo = X86::ST1; break;
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case 2: RegNo = X86::ST2; break;
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case 3: RegNo = X86::ST3; break;
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case 4: RegNo = X86::ST4; break;
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case 5: RegNo = X86::ST5; break;
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case 6: RegNo = X86::ST6; break;
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case 7: RegNo = X86::ST7; break;
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default: return Error(IntTok.getLoc(), "invalid stack index");
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}
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if (getParser().Lex().isNot(AsmToken::RParen))
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return Error(Parser.getTok().getLoc(), "expected ')'");
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EndLoc = Tok.getLoc();
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Parser.Lex(); // Eat ')'
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return false;
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}
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if (RegNo == 0)
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return Error(Tok.getLoc(), "invalid register name");
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EndLoc = Tok.getLoc();
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Parser.Lex(); // Eat identifier token.
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return false;
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}
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X86Operand *X86ATTAsmParser::ParseOperand() {
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switch (getLexer().getKind()) {
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default:
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// Parse a memory operand with no segment register.
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return ParseMemOperand(0, Parser.getTok().getLoc());
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case AsmToken::Percent: {
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// Read the register.
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unsigned RegNo;
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SMLoc Start, End;
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if (ParseRegister(RegNo, Start, End)) return 0;
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// If this is a segment register followed by a ':', then this is the start
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// of a memory reference, otherwise this is a normal register reference.
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if (getLexer().isNot(AsmToken::Colon))
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return X86Operand::CreateReg(RegNo, Start, End);
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getParser().Lex(); // Eat the colon.
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return ParseMemOperand(RegNo, Start);
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}
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case AsmToken::Dollar: {
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// $42 -> immediate.
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SMLoc Start = Parser.getTok().getLoc(), End;
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Parser.Lex();
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const MCExpr *Val;
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if (getParser().ParseExpression(Val, End))
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return 0;
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return X86Operand::CreateImm(Val, Start, End);
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}
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}
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}
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/// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
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/// has already been parsed if present.
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X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
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// We have to disambiguate a parenthesized expression "(4+5)" from the start
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// of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
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// only way to do this without lookahead is to eat the '(' and see what is
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// after it.
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const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
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if (getLexer().isNot(AsmToken::LParen)) {
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SMLoc ExprEnd;
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if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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// Unless we have a segment register, treat this as an immediate.
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if (SegReg == 0)
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return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
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return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
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}
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// Eat the '('.
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Parser.Lex();
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} else {
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// Okay, we have a '('. We don't know if this is an expression or not, but
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// so we have to eat the ( to see beyond it.
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SMLoc LParenLoc = Parser.getTok().getLoc();
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Parser.Lex(); // Eat the '('.
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if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
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// Nothing to do here, fall into the code below with the '(' part of the
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// memory operand consumed.
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} else {
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SMLoc ExprEnd;
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// It must be an parenthesized expression, parse it now.
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if (getParser().ParseParenExpression(Disp, ExprEnd))
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return 0;
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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// Unless we have a segment register, treat this as an immediate.
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if (SegReg == 0)
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return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
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return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
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}
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// Eat the '('.
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Parser.Lex();
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}
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}
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// If we reached here, then we just ate the ( of the memory operand. Process
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// the rest of the memory operand.
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|
unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
|
|
|
|
if (getLexer().is(AsmToken::Percent)) {
|
|
SMLoc L;
|
|
if (ParseRegister(BaseReg, L, L)) return 0;
|
|
}
|
|
|
|
if (getLexer().is(AsmToken::Comma)) {
|
|
Parser.Lex(); // Eat the comma.
|
|
|
|
// Following the comma we should have either an index register, or a scale
|
|
// value. We don't support the later form, but we want to parse it
|
|
// correctly.
|
|
//
|
|
// Not that even though it would be completely consistent to support syntax
|
|
// like "1(%eax,,1)", the assembler doesn't.
|
|
if (getLexer().is(AsmToken::Percent)) {
|
|
SMLoc L;
|
|
if (ParseRegister(IndexReg, L, L)) return 0;
|
|
|
|
if (getLexer().isNot(AsmToken::RParen)) {
|
|
// Parse the scale amount:
|
|
// ::= ',' [scale-expression]
|
|
if (getLexer().isNot(AsmToken::Comma)) {
|
|
Error(Parser.getTok().getLoc(),
|
|
"expected comma in scale expression");
|
|
return 0;
|
|
}
|
|
Parser.Lex(); // Eat the comma.
|
|
|
|
if (getLexer().isNot(AsmToken::RParen)) {
|
|
SMLoc Loc = Parser.getTok().getLoc();
|
|
|
|
int64_t ScaleVal;
|
|
if (getParser().ParseAbsoluteExpression(ScaleVal))
|
|
return 0;
|
|
|
|
// Validate the scale amount.
|
|
if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
|
|
Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
|
|
return 0;
|
|
}
|
|
Scale = (unsigned)ScaleVal;
|
|
}
|
|
}
|
|
} else if (getLexer().isNot(AsmToken::RParen)) {
|
|
// Otherwise we have the unsupported form of a scale amount without an
|
|
// index.
|
|
SMLoc Loc = Parser.getTok().getLoc();
|
|
|
|
int64_t Value;
|
|
if (getParser().ParseAbsoluteExpression(Value))
|
|
return 0;
|
|
|
|
Error(Loc, "cannot have scale factor without index register");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
// Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
|
|
if (getLexer().isNot(AsmToken::RParen)) {
|
|
Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
|
|
return 0;
|
|
}
|
|
SMLoc MemEnd = Parser.getTok().getLoc();
|
|
Parser.Lex(); // Eat the ')'.
|
|
|
|
return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
|
|
MemStart, MemEnd);
|
|
}
|
|
|
|
bool X86ATTAsmParser::
|
|
ParseInstruction(const StringRef &Name, SMLoc NameLoc,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
// The various flavors of pushf and popf use Requires<In32BitMode> and
|
|
// Requires<In64BitMode>, but the assembler doesn't yet implement that.
|
|
// For now, just do a manual check to prevent silent misencoding.
|
|
if (Is64Bit) {
|
|
if (Name == "popfl")
|
|
return Error(NameLoc, "popfl cannot be encoded in 64-bit mode");
|
|
else if (Name == "pushfl")
|
|
return Error(NameLoc, "pushfl cannot be encoded in 64-bit mode");
|
|
} else {
|
|
if (Name == "popfq")
|
|
return Error(NameLoc, "popfq cannot be encoded in 32-bit mode");
|
|
else if (Name == "pushfq")
|
|
return Error(NameLoc, "pushfq cannot be encoded in 32-bit mode");
|
|
}
|
|
|
|
// FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to
|
|
// represent alternative syntaxes in the .td file, without requiring
|
|
// instruction duplication.
|
|
StringRef PatchedName = StringSwitch<StringRef>(Name)
|
|
.Case("sal", "shl")
|
|
.Case("salb", "shlb")
|
|
.Case("sall", "shll")
|
|
.Case("salq", "shlq")
|
|
.Case("salw", "shlw")
|
|
.Case("repe", "rep")
|
|
.Case("repz", "rep")
|
|
.Case("repnz", "repne")
|
|
.Case("pushf", Is64Bit ? "pushfq" : "pushfl")
|
|
.Case("popf", Is64Bit ? "popfq" : "popfl")
|
|
.Case("retl", Is64Bit ? "retl" : "ret")
|
|
.Case("retq", Is64Bit ? "ret" : "retq")
|
|
.Case("setz", "sete")
|
|
.Case("setnz", "setne")
|
|
.Case("jz", "je")
|
|
.Case("jnz", "jne")
|
|
.Case("cmovcl", "cmovbl")
|
|
.Case("cmovcl", "cmovbl")
|
|
.Case("cmovnal", "cmovbel")
|
|
.Case("cmovnbl", "cmovael")
|
|
.Case("cmovnbel", "cmoval")
|
|
.Case("cmovncl", "cmovael")
|
|
.Case("cmovngl", "cmovlel")
|
|
.Case("cmovnl", "cmovgel")
|
|
.Case("cmovngl", "cmovlel")
|
|
.Case("cmovngel", "cmovll")
|
|
.Case("cmovnll", "cmovgel")
|
|
.Case("cmovnlel", "cmovgl")
|
|
.Case("cmovnzl", "cmovnel")
|
|
.Case("cmovzl", "cmovel")
|
|
.Default(Name);
|
|
|
|
// FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
|
|
const MCExpr *ExtraImmOp = 0;
|
|
if (PatchedName.startswith("cmp") &&
|
|
(PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
|
|
PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
|
|
unsigned SSEComparisonCode = StringSwitch<unsigned>(
|
|
PatchedName.slice(3, PatchedName.size() - 2))
|
|
.Case("eq", 0)
|
|
.Case("lt", 1)
|
|
.Case("le", 2)
|
|
.Case("unord", 3)
|
|
.Case("neq", 4)
|
|
.Case("nlt", 5)
|
|
.Case("nle", 6)
|
|
.Case("ord", 7)
|
|
.Default(~0U);
|
|
if (SSEComparisonCode != ~0U) {
|
|
ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
|
|
getParser().getContext());
|
|
if (PatchedName.endswith("ss")) {
|
|
PatchedName = "cmpss";
|
|
} else if (PatchedName.endswith("sd")) {
|
|
PatchedName = "cmpsd";
|
|
} else if (PatchedName.endswith("ps")) {
|
|
PatchedName = "cmpps";
|
|
} else {
|
|
assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
|
|
PatchedName = "cmppd";
|
|
}
|
|
}
|
|
}
|
|
Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
|
|
|
|
if (ExtraImmOp)
|
|
Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
|
|
// Parse '*' modifier.
|
|
if (getLexer().is(AsmToken::Star)) {
|
|
SMLoc Loc = Parser.getTok().getLoc();
|
|
Operands.push_back(X86Operand::CreateToken("*", Loc));
|
|
Parser.Lex(); // Eat the star.
|
|
}
|
|
|
|
// Read the first operand.
|
|
if (X86Operand *Op = ParseOperand())
|
|
Operands.push_back(Op);
|
|
else
|
|
return true;
|
|
|
|
while (getLexer().is(AsmToken::Comma)) {
|
|
Parser.Lex(); // Eat the comma.
|
|
|
|
// Parse and remember the operand.
|
|
if (X86Operand *Op = ParseOperand())
|
|
Operands.push_back(Op);
|
|
else
|
|
return true;
|
|
}
|
|
}
|
|
|
|
// FIXME: Hack to handle recognizing s{hr,ar,hl}? $1.
|
|
if ((Name.startswith("shr") || Name.startswith("sar") ||
|
|
Name.startswith("shl")) &&
|
|
Operands.size() == 3 &&
|
|
static_cast<X86Operand*>(Operands[1])->isImm() &&
|
|
isa<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm()) &&
|
|
cast<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm())->getValue() == 1) {
|
|
delete Operands[1];
|
|
Operands.erase(Operands.begin() + 1);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
|
|
StringRef IDVal = DirectiveID.getIdentifier();
|
|
if (IDVal == ".word")
|
|
return ParseDirectiveWord(2, DirectiveID.getLoc());
|
|
return true;
|
|
}
|
|
|
|
/// ParseDirectiveWord
|
|
/// ::= .word [ expression (, expression)* ]
|
|
bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
for (;;) {
|
|
const MCExpr *Value;
|
|
if (getParser().ParseExpression(Value))
|
|
return true;
|
|
|
|
getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
|
|
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
break;
|
|
|
|
// FIXME: Improve diagnostic.
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
/// LowerMOffset - Lower an 'moffset' form of an instruction, which just has a
|
|
/// imm operand, to having "rm" or "mr" operands with the offset in the disp
|
|
/// field.
|
|
static void LowerMOffset(MCInst &Inst, unsigned Opc, unsigned RegNo,
|
|
bool isMR) {
|
|
MCOperand Disp = Inst.getOperand(0);
|
|
|
|
// Start over with an empty instruction.
|
|
Inst = MCInst();
|
|
Inst.setOpcode(Opc);
|
|
|
|
if (!isMR)
|
|
Inst.addOperand(MCOperand::CreateReg(RegNo));
|
|
|
|
// Add the mem operand.
|
|
Inst.addOperand(MCOperand::CreateReg(0)); // Segment
|
|
Inst.addOperand(MCOperand::CreateImm(1)); // Scale
|
|
Inst.addOperand(MCOperand::CreateReg(0)); // IndexReg
|
|
Inst.addOperand(Disp); // Displacement
|
|
Inst.addOperand(MCOperand::CreateReg(0)); // BaseReg
|
|
|
|
if (isMR)
|
|
Inst.addOperand(MCOperand::CreateReg(RegNo));
|
|
}
|
|
|
|
// FIXME: Custom X86 cleanup function to implement a temporary hack to handle
|
|
// matching INCL/DECL correctly for x86_64. This needs to be replaced by a
|
|
// proper mechanism for supporting (ambiguous) feature dependent instructions.
|
|
void X86ATTAsmParser::InstructionCleanup(MCInst &Inst) {
|
|
if (!Is64Bit) return;
|
|
|
|
switch (Inst.getOpcode()) {
|
|
case X86::DEC16r: Inst.setOpcode(X86::DEC64_16r); break;
|
|
case X86::DEC16m: Inst.setOpcode(X86::DEC64_16m); break;
|
|
case X86::DEC32r: Inst.setOpcode(X86::DEC64_32r); break;
|
|
case X86::DEC32m: Inst.setOpcode(X86::DEC64_32m); break;
|
|
case X86::INC16r: Inst.setOpcode(X86::INC64_16r); break;
|
|
case X86::INC16m: Inst.setOpcode(X86::INC64_16m); break;
|
|
case X86::INC32r: Inst.setOpcode(X86::INC64_32r); break;
|
|
case X86::INC32m: Inst.setOpcode(X86::INC64_32m); break;
|
|
|
|
// moffset instructions are x86-32 only.
|
|
case X86::MOV8o8a: LowerMOffset(Inst, X86::MOV8rm , X86::AL , false); break;
|
|
case X86::MOV16o16a: LowerMOffset(Inst, X86::MOV16rm, X86::AX , false); break;
|
|
case X86::MOV32o32a: LowerMOffset(Inst, X86::MOV32rm, X86::EAX, false); break;
|
|
case X86::MOV8ao8: LowerMOffset(Inst, X86::MOV8mr , X86::AL , true); break;
|
|
case X86::MOV16ao16: LowerMOffset(Inst, X86::MOV16mr, X86::AX , true); break;
|
|
case X86::MOV32ao32: LowerMOffset(Inst, X86::MOV32mr, X86::EAX, true); break;
|
|
}
|
|
}
|
|
|
|
bool
|
|
X86ATTAsmParser::MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*>
|
|
&Operands,
|
|
MCInst &Inst) {
|
|
// First, try a direct match.
|
|
if (!MatchInstructionImpl(Operands, Inst))
|
|
return false;
|
|
|
|
// Ignore anything which is obviously not a suffix match.
|
|
if (Operands.size() == 0)
|
|
return true;
|
|
X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
|
|
if (!Op->isToken() || Op->getToken().size() > 15)
|
|
return true;
|
|
|
|
// FIXME: Ideally, we would only attempt suffix matches for things which are
|
|
// valid prefixes, and we could just infer the right unambiguous
|
|
// type. However, that requires substantially more matcher support than the
|
|
// following hack.
|
|
|
|
// Change the operand to point to a temporary token.
|
|
char Tmp[16];
|
|
StringRef Base = Op->getToken();
|
|
memcpy(Tmp, Base.data(), Base.size());
|
|
Op->setTokenValue(StringRef(Tmp, Base.size() + 1));
|
|
|
|
// Check for the various suffix matches.
|
|
Tmp[Base.size()] = 'b';
|
|
bool MatchB = MatchInstructionImpl(Operands, Inst);
|
|
Tmp[Base.size()] = 'w';
|
|
bool MatchW = MatchInstructionImpl(Operands, Inst);
|
|
Tmp[Base.size()] = 'l';
|
|
bool MatchL = MatchInstructionImpl(Operands, Inst);
|
|
Tmp[Base.size()] = 'q';
|
|
bool MatchQ = MatchInstructionImpl(Operands, Inst);
|
|
|
|
// Restore the old token.
|
|
Op->setTokenValue(Base);
|
|
|
|
// If exactly one matched, then we treat that as a successful match (and the
|
|
// instruction will already have been filled in correctly, since the failing
|
|
// matches won't have modified it).
|
|
if (MatchB + MatchW + MatchL + MatchQ == 3)
|
|
return false;
|
|
|
|
// Otherwise, the match failed.
|
|
return true;
|
|
}
|
|
|
|
|
|
extern "C" void LLVMInitializeX86AsmLexer();
|
|
|
|
// Force static initialization.
|
|
extern "C" void LLVMInitializeX86AsmParser() {
|
|
RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
|
|
RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
|
|
LLVMInitializeX86AsmLexer();
|
|
}
|
|
|
|
#include "X86GenAsmMatcher.inc"
|