llvm-project/llvm/test/CodeGen
Masoud Ataei 2d038370bb DAGCombiner optimization for pow(x,0.75) and pow(x,0.25) on double and single precision even in case massv function is asked
Here, I am proposing to add an special case for massv powf4/powd2 function (SIMD counterpart of powf/pow function in MASSV library) in MASSV pass to get later optimizations like conversion from pow(x,0.75) and pow(x,0.25) for double and single precision to sequence of sqrt's in the DAGCombiner in vector float case. My reason for doing this is: the optimized pow(x,0.75) and pow(x,0.25) for double and single precision to sequence of sqrt's is faster than powf4/powd2 on P8 and P9.

In case MASSV functions is called, and if the exponent of pow is 0.75 or 0.25, we will get the sequence of sqrt's and if exponent is not 0.75 or 0.25 we will get the appropriate MASSV function.

Reviewed By: steven.zhang

Tags: #LLVM #PowerPC

Differential Revision: https://reviews.llvm.org/D80744
2020-06-12 10:02:16 -04:00
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AArch64 [AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions. 2020-06-12 07:34:33 +01:00
AMDGPU [AMDGPU] Add G16 support to image instructions 2020-06-12 11:26:31 +02:00
ARC
ARM [ARM][MachineOutliner] Add NoLRSave mode. 2020-06-11 08:45:46 +02:00
AVR [AVR][test] Remove test for naked function containing a return. 2020-06-09 09:06:47 +01:00
BPF [BPF] fix incorrect type in BPFISelDAGToDAG readonly load optimization 2020-06-11 19:31:06 -07:00
Generic [Tests] Migrate a number of tests to gc-live bundle representation 2020-06-05 16:44:04 -07:00
Hexagon Simplify MachineVerifier's block-successor verification. 2020-06-06 22:30:51 -04:00
Inputs
Lanai
MIR [MachineVerifier] Verify that a DBG_VALUE has a debug location 2020-05-28 13:53:40 -07:00
MSP430
Mips RegAllocFast: Record internal state based on register units 2020-06-03 16:51:46 -04:00
NVPTX
PowerPC DAGCombiner optimization for pow(x,0.75) and pow(x,0.25) on double and single precision even in case massv function is asked 2020-06-12 10:02:16 -04:00
RISCV Add NoMerge MIFlag to avoid MIR branch folding 2020-05-29 12:31:06 -07:00
SPARC [SPARC] Lower fp16 ops to libcalls 2020-06-10 19:15:26 -07:00
SystemZ [CostModel] Unify Shuffle and InsertElement Costs 2020-06-10 09:13:34 +01:00
Thumb
Thumb2 [ARM] Add some MVE vecreduce tests. NFC 2020-06-09 12:07:19 +01:00
VE [VE] Support lowering to NND instruction 2020-06-09 10:18:14 +02:00
WebAssembly [WebAssembly] Make BR_TABLE non-duplicable 2020-06-11 15:11:45 -07:00
WinCFGuard
WinEH
X86 [DAG] foldAddSubOfSignBit - add support for non-uniform vector constants 2020-06-12 14:58:15 +01:00
XCore