Tim Northover d32f8e60bf ARM: sink atomic release barrier as far as possible into cmpxchg. ... DMB instructions can be expensive, so it's best to avoid them if possible. In atomicrmw operations there will always be an attempted store so a release barrier is always needed, but in the cmpxchg case we can delay the DMB until we know we'll definitely try to perform a store (and so need release semantics). In the strong cmpxchg case this isn't quite free: we must duplicate the LDREX instructions to skip the barrier on subsequent iterations. The basic outline becomes: ldrex rOld, [rAddr] cmp rOld, rDesired bne Ldone dmb Lloop: strex rRes, rNew, [rAddr] cbz rRes Ldone ldrex rOld, [rAddr] cmp rOld, rDesired beq Lloop Ldone: So we'll skip this version for strong operations in "minsize" functions. llvm-svn: 261568		2016-02-22 20:55:50 +00:00
..
ARM	ARM: sink atomic release barrier as far as possible into cmpxchg.	2016-02-22 20:55:50 +00:00
X86	[IR] Extend cmpxchg to allow pointer type operands	2016-02-19 00:06:41 +00:00